PIC18F86K22-I/PTRSL Microchip Technology, PIC18F86K22-I/PTRSL Datasheet - Page 250

• Manufacturer Part Number: PIC18F86K22-I/PTRSL
• Description: MCU PIC 64K FLASH XLP 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K22-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3862Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
19.3
In Compare mode, the 16-bit CCPR4 register value is
constantly compared against the Timer register pair
value selected in the CCPTMR1 register. When a
match occurs, the CCP4 pin can be:
• Driven high
• Driven low
• Toggled (high-to-low or low-to-high)
• Unchanged (that is, reflecting the state of the I/O
The action on the pin is based on the value of the mode
select bits (CCP4M<3:0>). At the same time, the
interrupt flag bit, CCP4IF, is set.
Figure 19-2 gives the Compare mode block diagram
19.3.1
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
19.3.2
If the CCP module is using the compare feature in
conjunction with any of the Timer1/3/5/7 timers, the
timers must be running in Timer mode or Synchronized
Counter mode. In Asynchronous Counter mode, the
compare operation may not work.
DS39960B-page 250
latch)
Note:
Note:
Compare Mode
CCP PIN CONFIGURATION
Clearing the CCP4CON register will force
the RC1 or RE7 compare output latch
(depending on device configuration) to the
default low level. This is not the PORTC or
PORTE I/O data latch.
TIMER1/3/5/7 MODE SELECTION
Details of the timer assignments for the
CCP modules are given in Table 19-2 and
Table 19-3.
Preliminary
19.3.3
When the Generate Software Interrupt mode is chosen
(CCP4M<3:0> = 1010), the CCP4 pin is not affected.
Only a CCP interrupt is generated, if enabled, and the
CCP4IE bit is set.
19.3.4
Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the
(CCP4M<3:0> = 1011).
For either CCP module, the Special Event Trigger resets
the Timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programmable
period register for either timer.
The Special Event Trigger for CCP4 cannot start an
A/D conversion.
Note:
Compare
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
The Special Event Trigger of ECCP2 can start
an A/D conversion, but the A/D Converter
must be enabled. For more information, see
Section 19.0
(CCP) Modules”.
Special
 2010 Microchip Technology Inc.
Event
“Capture/Compare/PWM
Trigger
mode