PIC18F86K22-I/PTRSL Microchip Technology, PIC18F86K22-I/PTRSL Datasheet - Page 243

• Manufacturer Part Number: PIC18F86K22-I/PTRSL
• Description: MCU PIC 64K FLASH XLP 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K22-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3862Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.0
PIC18F87K22 family devices have seven CCP
(Capture/Compare/PWM) modules, designated CCP4
through CCP10. All the modules implement standard
Capture, Compare and Pulse-Width Modulation (PWM)
modes.
REGISTER 19-1:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-4
bit 3-0
Note 1:
Note:
U-0
—
2:
CAPTURE/COMPARE/PWM
(CCP) MODULES
indicates the item’s association with the
control register is named CCPxCON and
The CCP9 and CCP10 modules are not available on the devices with 32 Kbytes of program memory
(PIC18FX5K22).
CCPxM<3:0> = 1011 will only reset the timer and not start A/D conversion on CCPx match.
Throughout this section, generic references
are used for register and bit names that are
the same, except for an ‘x’ variable that
specific CCP module. For example, the
refers to CCP4CON through CCP10CON.
Unimplemented: Read as ‘0’
DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCPx Module
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight
Most Significant bits (DCx<9:2>) of the duty cycle are found in CCPRxL.
CCPxM<3:0>: CCPx Module Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode: every falling edge
0101 = Capture mode: every rising edge
0110 = Capture mode: every 4th rising edge
0111 = Capture mode: every 16th rising edge
1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set)
1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set)
1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin
1011 = Compare mode: Special Event Trigger; reset timer on CCPx match (CCPxIF bit is set)
11xx = PWM mode
U-0
—
CCPxCON: CCPx CONTROL REGISTER (CCP4-CCP10 MODULES)
reflects I/O state)
W = Writable bit
‘1’ = Bit is set
DCxB1
R/W-0
DCxB0
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F87K22 FAMILY
CCPxM3
(2)
R/W-0
Each CCP module contains a 16-bit register that can
operate as a 16-bit Capture register, a 16-bit Compare
register or a PWM Master/Slave Duty Cycle register.
For the sake of clarity, all CCP module operation in the
following sections is described with respect to CCP4,
but is equally applicable to CCP5 through CCP10.
Note:
(2)
The CCP9 and CCP10 modules are
disabled on the devices with 32 Kbytes of
program memory (PIC18FX5K22).
CCPxM2
R/W-0
(2)
x = Bit is unknown
CCPxM1
R/W-0
DS39960B-page 243
(2)
(1)
CCPxM0
R/W-0
bit 0
(2)