PIC18F86K22-I/PTRSL Microchip Technology, PIC18F86K22-I/PTRSL Datasheet - Page 63

• Manufacturer Part Number: PIC18F86K22-I/PTRSL
• Description: MCU PIC 64K FLASH XLP 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K22-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3862Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 4-1:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
CCP10MD
R/W-0
2:
3:
(1,3)
Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
RTCCMD can only be set to ‘1’ after an EECON2 unlock sequence. Refer to Section 18.0 “Real-Time
Clock and Calendar (RTCC)” for the unlock sequence (Example 18-1).
Unimplemented on devices with 64 pins (PIC18F6XK22).
CCP10MD: PMD CCP10 Enable/Disable bit
1 = Peripheral Module Disable (PMD) is enabled for CCP10, disabling all of its clock sources
0 = PMD is disabled for CCP10
CCP9MD: PMD CCP9 Enable/Disable bit
1 = Peripheral Module Disable (PMD) is enabled for CCP9, disabling all of its clock sources
0 = PMD is disabled for CCP9
CCP8MD: PMD CCP8 Enable/Disable bit
1 = Peripheral Module Disable (PMD) is enabled for CCP8, disabling all of its clock sources
0 = PMD is disabled for CCP8
CCP7MD: PMD CCP7 Enable/Disable bit
1 = Peripheral Module Disable (PMD) is enabled for CCP7, disabling all of its clock sources
0 = PMD is disabled for CCP7
CCP6MD: PMD CCP6 Enable/Disable bit
1 = Peripheral Module Disable (PMD) is enabled for CCP6, disabling all of its clock sources
0 = PMD is disabled for CCP6
CCP5MD: PMD CCP5 Enable/Disable bit
1 = Peripheral Module Disable (PMD) is enabled for CCP5, disabling all of its clock sources
0 = PMD is disabled for CCP5
CCP4MD: PMD CCP4 Enable/Disable bit
1 = Peripheral Module Disable (PMD) is enabled for CCP4, disabling all of its clock sources
0 = PMD is disabled for CCP4
TMR12MD
1 = PMD is enabled and all TMR12MD clock sources are disabled
0 = PMD is disabled and TMR12MD is enabled
CCP9MD
R/W-0
PMD3: PERIPHERAL MODULE DISABLE REGISTER 3
(1,3)
(1)
: TMR12MD Disable bit
W = Writable bit
‘1’ = Bit is set
CCP8MD
R/W-0
(1,3)
CCP7MD
R/W-0
Preliminary
(1,3)
(1,3)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F87K22 FAMILY
(1,3)
CCP6MD
R/W-0
CCP5MD
R/W-0
(2)
x = Bit is unknown
CCP4MD
R/W-0
DS39960B-page 63
TMR12MD
R/W-0
bit 0
(1)