PIC18F86K22-I/PTRSL Microchip Technology, PIC18F86K22-I/PTRSL Datasheet - Page 165

• Manufacturer Part Number: PIC18F86K22-I/PTRSL
• Description: MCU PIC 64K FLASH XLP 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K22-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3862Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.1.3
The output pins for several peripherals are also
equipped with a configurable, open-drain output option.
This allows the peripherals to communicate with
external digital logic, operating at a higher voltage
level, without the use of level translators.
The open-drain option is implemented on port pins
specifically associated with the data and clock outputs
of the USARTs, the MSSP module (in SPI mode) and
the CCP modules. This option is selectively enabled by
setting the open-drain control bits in the registers
ODCON1, ODCON2 and ODCON3.
When the open-drain option is required, the output pin
must also be tied through an external pull-up resistor
provided by the user to a higher voltage level, up to 5V
(Figure 12-2). When a digital logic high signal is output,
it is pulled up to the higher voltage level.
REGISTER 12-2:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4-1
bit 0
SSP1OD
R/W-0
OPEN-DRAIN OUTPUTS
SSP1OD: MSSP1 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
CCP2OD: ECCP2 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
CCP1OD: CCP10 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
Unimplemented: Read as ‘0’
SSP2OD: MSSP2 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
CCP2OD
R/W-0
ODCON1: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 1
W = Writable bit
‘1’ = Bit is set
CCP1OD
R/W-0
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F87K22 FAMILY
FIGURE 12-2:
U-0
—
3.3V
V
DD
PIC18F87K22
U-0
—
(at logic ‘1’)
USING THE OPEN-DRAIN
OUTPUT (USART SHOWN
AS EXAMPLE)
TX
x = Bit is unknown
X
3.3V
U-0
—
DS39960B-page 165
+5V
SSP2OD
R/W-0
5V
bit 0