PIC18F86K22-I/PTRSL Microchip Technology, PIC18F86K22-I/PTRSL Datasheet - Page 211

• Manufacturer Part Number: PIC18F86K22-I/PTRSL
• Description: MCU PIC 64K FLASH XLP 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K22-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3862Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.1
The Timer3/5/7 Gate Control register (TxGCON),
provided in Register 14-2, is used to control the Timerx
gate.
REGISTER 16-2:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
Note 1:
TMRxGE
R/W-0
2:
Timer3/5/7 Gate Control Register
Programming the TxGCON prior to TxCON is recommended.
Timer(x+1) will be Timer4/6/8 for Timerx (Timer3/5/7), respectively.
TMRxGE: Timerx Gate Enable bit
If TMRxON = 0:
This bit is ignored.
If TMRxON = 1:
1 = Timerx counting is controlled by the Timerx gate function
0 = Timerx counts regardless of Timerx gate function
TxGPOL: Timerx Gate Polarity bit
1 = Timerx gate is active-high (Timerx counts when gate is high)
0 = Timerx gate is active-low (Timerx counts when gate is low)
TxGTM: Timerx Gate Toggle Mode bit
1 = Timerx Gate Toggle mode is enabled.
0 = Timerx Gate Toggle mode is disabled and toggle flip-flop is cleared
Timerx gate flip-flop toggles on every rising edge.
TxGSPM: Timerx Gate Single Pulse Mode bit
1 = Timerx Gate Single Pulse mode is enabled and is controlling Timerx gate
0 = Timerx Gate Single Pulse mode is disabled
TxGGO/TxDONE: Timerx Gate Single Pulse Acquisition Status bit
1 = Timerx gate single pulse acquisition is ready, waiting for an edge
0 = Timerx gate single pulse acquisition has completed or has not been started
This bit is automatically cleared when TxGSPM is cleared.
TxGVAL: Timerx Gate Current State bit
Indicates the current state of the Timerx gate that could be provided to TMRxH:TMRxL. Unaffected by the
Timerx Gate Enable (TMRxGE) bit.
TxGSS<1:0>: Timerx Gate Source Select bits
11 = Comparator 2 output
10 = Comparator 1 output
01 = TMR(x+1) to match PR(x+1) output
00 = Timer1 gate pin
The Watchdog Timer oscillator is turned on if TMRxGE = 1, regardless of the state of TMRxON.
TxGPOL
R/W-0
TxGCON: TIMERx GATE CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
TxGTM
R/W-0
TxGSPM
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
(2)
‘0’ = Bit is cleared
TxGGO/TxDONE
PIC18F87K22 FAMILY
R/W-0
TxGVAL
(1)
R-x
x = Bit is unknown
TxGSS1
R/W-0
DS39960B-page 211
TxGSS0
R/W-0
bit 0