PIC18F86K22-I/PTRSL Microchip Technology, PIC18F86K22-I/PTRSL Datasheet - Page 171

• Manufacturer Part Number: PIC18F86K22-I/PTRSL
• Description: MCU PIC 64K FLASH XLP 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K22-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3862Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 12-3:
TABLE 12-4:
 2010 Microchip Technology Inc.
RB3/INT3/CTED2/
ECCP2/P2A
RB4/KBI0
RB5/KBI1/T3CKI/
T1G
RB6/KBI2/PGC
RB7/KBI3/PGD
Legend:
Note 1:
PORTB
LATB
TRISB
INTCON
INTCON2
INTCON3
ODCON1
Legend:
Name
Pin Name
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared and in Extended Microcontroller mode.
Shaded cells are not used by PORTB.
GIE/GIEH
SSP1OD
TRISB7
INT2IP
LATB7
RBPU
PORTB FUNCTIONS (CONTINUED)
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7
RB7
Function
ECCP2
CTED2
T3CKI
INT3
KBI0
KBI1
KBI2
PGC
KBI3
PGD
RB3
RB4
RB5
T1G
RB6
RB7
P2A
(1)
PEIE/GIEL
INTEDG0
CCP2OD
TRISB6
LATB6
INT1IP
Bit 6
RB6
Setting
TRIS
0
1
1
x
0
1
0
0
1
1
0
1
1
x
x
0
1
1
x
0
1
1
x
x
INTEDG1
CCP1OD
TMR0IE
TRISB5
INT3IE
LATB5
I/O
Bit 5
O
O
O
O
O
O
O
O
RB5
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Preliminary
Type
DIG
TTL
DIG
DIG
DIG
TTL
TTL
DIG
TTL
TTL
DIG
TTL
TTL
DIG
TTL
TTL
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
INTEDG2
TRISB4
INT0IE
INT2IE
LATB4
Bit 4
RB4
LATB<3> data output.
PORTB<3> data input; weak pull-up when RBPU bit is cleared.
External Interrupt 3 input.
CTMU Edge 2 input.
ECCP2 compare output and ECCP2 PWM output.
Takes priority over port data.
ECCP2 capture input.
ECCP2 Enhanced PWM output, Channel A.
May be configured for tri-state during Enhanced PWM shutdown
events. Takes priority over port data.
LATB<4> data output.
PORTB<4> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-pin change.
LATB<5> data output.
PORTB<5> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-pin change.
Timer3 clock input.
Timer1 external clock gate input.
LATB<6> data output.
PORTB<6> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-pin change.
Serial execution (ICSP™) clock input for ICSP and ICD operation.
LATB<7> data output.
PORTB<7> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-pin change.
Serial execution data output for ICSP and ICD operation.
Serial execution data input for ICSP and ICD operation.
—
PIC18F87K22 FAMILY
INTEDG3
TRISB3
INT1IE
LATB3
RBIE
Bit 3
RB3
—
TMR0IF
TMR0IP
TRISB2
Description
LATB2
INT3IF
Bit 2
RB2
—
TRISB1
INT0IF
INT3IP
INT2IF
LATB1
Bit 1
RB1
—
DS39960B-page 171
SSP2OD
TRISB0
INT1IF
LATB0
RBIP
Bit 0
RBIF
RB0