PIC18F86K22-I/PTRSL Microchip Technology, PIC18F86K22-I/PTRSL Datasheet - Page 543

• Manufacturer Part Number: PIC18F86K22-I/PTRSL
• Description: MCU PIC 64K FLASH XLP 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K22-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3862Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

 2010 Microchip Technology Inc.
Example SPI Slave Mode (CKE = 0) ........................ 513
Example SPI Slave Mode (CKE = 1) ........................ 514
External Clock........................................................... 501
External Memory Bus for SLEEP (Extended
External Memory Bus for TBLRD (Extended
Fail-Safe Clock Monitor (FSCM) ............................... 423
First Start Bit Timing ................................................. 313
Full-Bridge PWM Output ........................................... 268
Half-Bridge PWM Output .................................. 266, 273
High-Voltage Detect Operation (VDIRMAG = 1)....... 381
HLVD Characteristics................................................ 508
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Low-Voltage Detect Operation (VDIRMAG = 0) ....... 380
MSSP I
MSSP I
Parallel Slave Port (PSP) Read ................................ 189
Parallel Slave Port (PSP) Write ................................ 188
Program Memory Read............................................. 505
PWM Auto-Shutdown with Auto-Restart
PWM Auto-Shutdown with Firmware Restart
PWM Direction Change ............................................ 269
PWM Direction Change at Near 100%
PWM Output ............................................................. 253
PWM Output (Active-High)........................................ 264
PWM Output (Active-Low) ........................................ 265
Repeated Start Condition.......................................... 314
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................. 342
Slave Synchronization .............................................. 285
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode).......................................... 284
SPI Mode (Slave Mode, CKE = 0) ............................ 286
SPI Mode (Slave Mode, CKE = 1) ............................ 286
Steering Event at Beginning of Instruction
Steering Event at End of Instruction
Synchronous Reception (Master Mode, SREN) ....... 345
Synchronous Transmission....................................... 343
Synchronous Transmission (Through TXEN) ........... 344
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Acknowledge Sequence ..................................... 318
C Bus Data ............................................................. 516
C Bus Start/Stop Bits.............................................. 515
C Master Mode (7 or 10-Bit Transmission) ............ 316
C Master Mode (7-Bit Reception)........................... 317
C Slave Mode (10-Bit Reception, SEN = 0,
C Slave Mode (10-Bit Reception, SEN = 0) ........... 302
C Slave Mode (10-Bit Reception, SEN = 1) ........... 307
C Slave Mode (10-Bit Transmission)...................... 303
C Slave Mode (7-bit Reception, SEN = 0,
C Slave Mode (7-Bit Reception, SEN = 0) ............. 298
C Slave Mode (7-Bit Reception, SEN = 1) ............. 306
C Slave Mode (7-Bit Transmission)........................ 300
C Slave Mode General Call Address Sequence
C Stop Condition Receive or Transmit Mode ......... 318
Microcontroller Mode) ............................... 126, 128
Microcontroller Mode) ............................... 126, 128
ADMSK = 01001).............................................. 301
ADMSK = 01011).............................................. 299
(7 or 10-Bit Addressing Mode) .......................... 308
Enabled (PxRSEN = 1) ..................................... 272
(PxRSEN = 0) ................................................... 272
Duty Cycle ........................................................ 270
Timer (OST) and Power-up Timer (PWRT) ...... 507
(STRSYNC = 1) ................................................ 276
(STRSYNC = 0) ................................................ 276
V
DD
2
2
C Bus Data.................................................. 517
C Bus Start/Stop Bits .................................. 517
Rise > T
PWRT
) ............................................ 75
DD
,
Preliminary
PIC18F87K22 FAMILY
Timing Diagrams and Specifications
Top-of-Stack Access........................................................... 87
TSTFSZ ............................................................................ 469
Time-out Sequence on Power-up (MCLR Not
Time-out Sequence on Power-up (MCLR Not
Time-out Sequence on Power-up (MCLR
Timer Pulse Generation............................................ 240
Timer0 and Timer1 External Clock ........................... 509
Timer1 Gate Count Enable Mode............................. 202
Timer1 Gate Single Pulse Mode............................... 204
Timer1 Gate Single Pulse/Toggle
Timer1 Gate Toggle Mode........................................ 203
Timer3/5/7 Gate Count Enable Mode....................... 215
Timer3/5/7 Gate Single Pulse Mode......................... 217
Timer3/5/7 Gate Single Pulse/Toggle
Timer3/5/7 Gate Toggle Mode.................................. 216
Transition for Entry to Idle Mode ................................ 61
Transition for Entry to SEC_RUN Mode ..................... 57
Transition for Entry to Sleep Mode ............................. 60
Transition for Two-Speed Start-up
Transition for Wake from Idle to Run Mode................ 61
Transition for Wake from Sleep (HSPLL) ................... 60
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode...................................... 59
Capture/Compare/PWM Requirements.................... 510
CLKO and I/O Requirements............................ 503, 505
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Mode Requirements (Master Mode,
Example SPI Mode Requirements (Master Mode,
Example SPI Mode Requirements (Slave Mode,
Example SPI Slave Mode Requirements
External Clock Requirements ................................... 501
HLVD Characteristics ............................................... 508
I
I
Internal RC Accuracy (INTOSC)............................... 502
MSSP I
MSSP I
PLL Clock ................................................................. 502
Program Memory Write Requirements ..................... 506
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External
2
2
C Bus Data Requirements (Slave Mode) ............... 516
C Bus Start/Stop Bits Requirements
Tied to V
Tied to V
Tied to V
Combined Mode ............................................... 205
Combined Mode ............................................... 218
(INTOSC to HSPLL) ......................................... 421
PRI_RUN Mode.................................................. 59
PRI_RUN Mode (HSPLL) ................................... 57
Requirements ................................................... 519
Requirements ................................................... 519
CKE = 0)........................................................... 511
CKE = 1)........................................................... 512
CKE = 0)........................................................... 513
(CKE = 1).......................................................... 514
(Slave Mode) .................................................... 515
Timer, Power-up Timer and Brown-out
Reset Requirements......................................... 507
Clock Requirements ......................................... 509
2
2
C Bus Data Requirements .......................... 518
C Bus Start/Stop Bits Requirements........... 517
DD
DD
DD
), Case 1 .......................................... 75
), Case 2 .......................................... 75
, V
DD
Rise T
PWRT
) ........................... 74
DS39960B-page 543