PIC18F86K22-I/PTRSL Microchip Technology, PIC18F86K22-I/PTRSL Datasheet - Page 219

• Manufacturer Part Number: PIC18F86K22-I/PTRSL
• Description: MCU PIC 64K FLASH XLP 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K22-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3862Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.6
The TMRx register pair (TMRxH:TMRxL) increments
from 0000h to FFFFh and overflows to 0000h. The
Timerx interrupt, if enabled, is generated on overflow
and is latched in the interrupt flag bit, TMRxIF.
Table 16-3 gives each module’s flag bit.
TABLE 16-3:
This interrupt can be enabled or disabled by setting or
clearing the TMRxIE bit, respectively. Table 16-4 gives
each module’s enable bit.
TABLE 16-4:
 2010 Microchip Technology Inc.
Timer Module
Timer Module
3
5
7
3
5
7
Timer3/5/7 Interrupt
TIMER3/5/7 INTERRUPT
FLAG BITS
TIMER3/5/7 INTERRUPT
ENABLE BITS
PIR2<1>
PIR5<1>
PIR5<3>
PIE2<1>
PIE5<1>
PIE5<3>
Flag Bit
Flag Bit
Preliminary
PIC18F87K22 FAMILY
16.7
If the ECCP modules are configured to use Timerx and
to generate a Special Event Trigger in Compare mode
(CCPxM<3:0> = 1011), this signal will reset Timerx. The
trigger from ECCP2 will also start an A/D conversion if
the A/D module is enabled (For more information, see
Section 20.3.4 “Special Event Trigger”.)
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPRxH:CCPRxL register
pair effectively becomes a Period register for Timerx.
If Timerx is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timerx coincides with a
Special Event Trigger from an ECCP module, the write
will take precedence.
Note:
Note:
Resetting Timer3/5/7 Using the
ECCP Special Event Trigger
The Special Event Triggers from the
ECCPx module will only clear the TMR3
register’s content, but not set the TMR3IF
interrupt flag bit (PIR1<0>).
The CCP and ECCP modules use Timers,
1 through 8, for some modes. The assign-
ment of a particular timer to a CCP/ECCP
module is determined by the Timer to CCP
enable bits in the CCPTMRSx registers.
For more details, see Register 20-2,
Register 19-2 and Register 19-3.
DS39960B-page 219