EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 106

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–14
Arria II GX PLL Hardware Overview
Figure 5–10. Arria II GX PLL Block Diagram
Notes to
(1) There are seven PLL output counters in Arria II GX devices.
(2) This is the VCO post-scale counter
Arria II GX Device Handbook, Volume 1
Dedicated clock inputs
from adjacent PLL
GCLK/RCLK
Cascade input
Figure
pfdena
5–10:
1
4
Table 5–8. Arria II GX PLL Features (Part 2 of 2)
Figure 5–10
Arria II GX PLL.
You can drive the GCLK or RCLK clock input with an output from another PLL, a
pin-driven GCLK or RCLK, or through a clock control block, provided the clock
control block is fed by an output from another PLL or a pin driven dedicated GCLK or
RCLK. An internally-generated global signal or general purpose I/O (GPIO) pin
cannot drive the PLL.
Input clock switchover
Notes to
(1) PLL_5 and PLL_6 do not have dedicated clock outputs.
(2) The same PLL clock output drives three single-ended or three differential I/O pairs. This is only supported in
(3) This is applicable only if the input clock jitter is within the input jitter tolerance specifications.
(4) The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For
inclk0
inclk1
PLL_1 and PLL_3 of EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices.
degree increments, the Arria II GX device can shift all output frequencies in increments of at least 45°. Smaller
degree increments are possible depending on the frequency and C counter value.
Table
Switchover
K
Clock
Block
.
shows a simplified block diagram of the major components of the
5–8:
Feature
÷n
clkswitch
clkbad0
clkbad1
activeclock
PFD
Circuit
Lock
CP
Yes
locked
LF
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
VCO
8
no compensation mode
ZDB mode
LVDS Compensation mode
Source Synchronous, normal modes
÷2
(2)
To DPA block on
Right PLLs
Arria II GX PLLs
/2, /4
8
8
© July 2010 Altera Corporation
÷C0
÷C1
÷C2
÷C3
÷Cn
÷m
(1)
PLLs in Arria II GX Devices
Casade output
to adjacent PLL
External clock outputs
DIFFCLK network
GCLK/RCLK network
GCLKs
RCLKs
DIFFCLK from
Right PLLs
LOAD_EN from
Right PLLs
External
memory
interface DLL
External clock
outputs