EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 231

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Fast Passive Parallel Configuration
Figure 9–3. Multiple-Device FPP Configuration Using an External Host When Both Devices Receive the Same Data
Notes to
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Arria II GX devices in the chain. V
(2) The MSEL pin settings vary for different configuration voltage standards and POR delay. To configure MSEL[3..0], refer to
© July 2010
to meet the V
I/Os with V
page
(MAX II Device or
Microprocessor)
Figure
External Host
ADDR DATA[7..0]
9–7.
Altera Corporation
Memory
CCIO
f
9–3:
IH
specification of the I/O standard on the device and external host. Altera recommends that you power up all configuration system's
for I/O banks 3C.
Figure 9–3
receiving the same configuration data.
You can use a single configuration chain to configure Arria II GX devices with other
Altera devices that support FPP configuration. To ensure that all devices in the chain
complete configuration at the same time, or that an error flagged by one device
initiates reconfiguration in all devices, tie all device CONF_DONE and nSTATUS pins
together.
For more information about configuring multiple Altera devices in the same
configuration chain, refer to the
volume 2 of the Configuration Handbook.
FPP Configuration Timing
Figure 9–4
device as an external host. This waveform shows timing when the decompression and
design security features are not enabled.
V
10 kΩ
CCIO
(1)
shows a multi-device FPP configuration when both Arria II GX devices are
shows the timing waveform for FPP configuration when using a MAX II
V
CCIO
10 kΩ
(1)
GND
Arria II GX Device 1
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
DCLK
Configuring Mixed Altera FPGA Chains
MSEL[3..0]
nCEO
N.C.
(2)
Arria II GX Device Handbook, Volume 1
GND
Arria II GX Device 2
nCE
CONF_DONE
nSTATUS
DATA[7..0]
nCONFIG
DCLK
CCIO
chapter in
must be high enough
MSEL[3..0]
Table 9–2 on
nCEO
9–11
N.C.
(2)