EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 160

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–2
Figure 7–1. External Memory Interface Datapath Overview
Notes to
(1) You can bypass each register block.
(2) Shaded blocks are implemented in the I/O element (IOE).
(3) The memory blocks used for each memory interface may differ slightly.
(4) These signals may be bidirectional or unidirectional, depending on the memory standard. When bidirectional, the signal is active during both read
Arria II GX Memory Interfaces Pin Support
Arria II GX Device Handbook, Volume 1
and write operations.
Clock Management & Reset
Figure
f
7–1:
Resynchronization Clock
DQ Write Clock
DQS Write Clock
Figure 7–1
A typical memory interface requires data (D, Q, or DQ), data strobe (DQS/CQ and
DQSn/CQn), address, command, and clock pins. Some memory interfaces use data
mask (DM or BWSn) pins to enable write masking. This section describes how
Arria II GX devices support all these pins.
The DDR3, DDR2, and DDR SDRAM devices use CK and CK# signals to capture the
address and command signals. You can generate these signals to mimic the write-data
strobe with Arria II GX DDR I/O registers (DDIOs) to ensure that timing
relationships between the CK/CK# and DQS signals (t
DDR2, and DDR SDRAM devices) are met. The QDR II+/QDR II SRAM devices use
the same clock (K/K#) to capture the write data, address, and command signals.
For more information about pin location requirements and pin connections between
an Arria II GX device and an external memory device, refer to the
Pin Planning
shows a memory interface datapath overview.
in volume 2 of the External Memory Interface Handbook.
Internal Memory (3)
Postamble Enable
Postamble Clock
(Note
2n
Synchronization
1),
Postamble
Registers
Control
Circuit
DLL
Chapter 7: External Memory Interfaces in Arria II GX Devices
(2)
2n
2
2n
DQS Enable
DDR Output
DQS Logic
DDR Output
and Output
DDR Input
and Output
Registers
Registers
Registers
Enable
Circuit
Enable
Block
DQSS
Arria II GX Memory Interfaces Pin Support
Arria II GX FPGA
, t
DSS
© July 2010 Altera Corporation
, and t
Section I. Device and
n
n
DSH
in DDR3,
DQS (Read) (4)
DQ (Read) (4)
DQ (Write) (4)
DQS (Write) (4)
Memory