EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 27

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Introduction
Logic Array Blocks
Figure 2–1. Arria II GX LAB Structure
© June 2009 Altera Corporation
AIIGX51002-1.1
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
R20
R4
This chapter describes the features of the logic array block (LAB) in the Arria
core fabric. The logic array block is composed of basic building blocks known as
adaptive logic modules (ALMs) that you can configure to implement logic functions,
arithmetic functions, and register functions.
This chapter contains the following sections:
■
■
Figure 2–1
“Logic Array Blocks” on page 2–1
“Adaptive Logic Modules” on page 2–4
Local Interconnect
shows the Arria II GX LAB structure and the LAB interconnects.
2. Logic Array Blocks and Adaptive Logic
LAB
C4
& LABs, & from Above by Row Interconnect
from Either Side by Column Interconnect
C12
Local Interconnect is Driven
Modules in Arria II GX Devices
Row Interconnects of
Variable Speed & Length
MLAB
ALMs
Arria II GX Device Handbook, Volume 1
Column Interconnects of
Variable Speed & Length
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
®
II GX