EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 107

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II GX Devices
PLLs in Arria II GX Devices
Figure 5–11. External Clock Outputs for Arria II GX PLLs
Notes to
(1) You can feed these clock output pins with any one of the C[6..0], and m counters.
(2) The PLL<#>_CLKOUT<#>p and PLL<#>_CLKOUT<#>n pins can be either single-ended or pseudo-differential clock outputs. The Arria II GX
(3) These external clock enable signals are available only when you use the ALTCLKCTRL megafunction.
© July 2010
PLL only routes single-ended I/Os to PLL<#>CLKOUT<#>p pins, while you can use PLL<#>_CLKOUT<#>n pins as user I/Os.
Figure
Altera Corporation
f
5–11:
Arria II GX
PLLs
PLL Clock I/O Pins
Each PLL supports one of the following clock I/O pin configurations:
■
■
Figure 5–11
Any of the output counters (C[6..0]) or the M counter can feed the dedicated
external clock outputs, as shown in
can drive all the output pins available from a given PLL.
Each pin of a single-ended output pair can either be in-phase or 180° out-of-phase.
The Quartus II software places the NOT gate in your design into the IOE to
implement a 180° phase with respect to the other pin in the pair. The clock output pin
pairs support the same I/O standards as standard output pins, as well as LVDS_E_3R,
LVPECL, differential high-speed transceiver logic (HSTL), and differential SSTL.
To determine which I/O standards are supported by the PLL clock input and output
pins, refer to the
PLL<#>_CLKOUT<#>p (1), (2)
One single-ended I/O or one differential I/O pair.
Three single-ended I/O or three differential I/O pairs (this is only supported in
PLL_1 and PLL_3 of EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260
devices). You can only access one differential I/O pair or one single-ended pin at a
time.
clkena0 (3)
C0
C1
C2
C3
C4
C5
C6
m
shows the clock I/O pins associated with Arria II GX PLLs.
I/O Features in Arria II GX Devices
clkena1 (3)
PLL<#>_CLKOUT<#>n (1), (2)
Figure
5–11. Therefore, one counter or frequency
Internal Logic
chapter.
Arria II GX Device Handbook, Volume 1
5–15