EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 59

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EP2AGX95EF29C4N

Manufacturer Part Number
EP2AGX95EF29C4N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr

Specifications of EP2AGX95EF29C4N

Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

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Chapter 3: Memory Blocks in Arria II GX Devices
Document Revision History
Power-Up Conditions and Memory Initialization
Power Management
Document Revision History
Table 3–7. Document Revision History
© November 2009
November 2009, v2.0
June 2009, v1.1
February 2009, v1.0
Date and Document
Version
f
Altera Corporation
Mixed-port read-during-write is not supported when two different clocks are used in
a dual-port RAM. The output value is unknown during a dual-clock mixed-port
read-during-write operation.
M9K memory block outputs power up to zero (cleared), regardless of whether the
output registers are used or bypassed. MLABs power up to zero if output registers are
used and power up reading the memory contents if output registers are not used. The
Quartus II software initializes the RAM cells to zero unless there is a .mif specified.
All memory blocks support initialization using a .mif. You can create .mif files in the
Quartus II software and specify their use with the RAM MegaWizard Plug-In
Manager when instantiating a memory in your design. Even if a memory is
pre-initialized (for example, using a .mif), it still powers up with its outputs cleared.
For more information about .mif files, refer to the
the
Arria II GX memory block clock-enables allow you to control clocking of each
memory block to reduce AC-power consumption. Use the read-enable signal to
ensure that read operations only occur when you need them to. If your design does
not require read-during-write, you can reduce your power consumption by
de-asserting the read-enable signal during write operations or any period when no
memory operations occur.
The Quartus II software automatically places any unused memory blocks in low
power mode to reduce static power.
Table 3–7
Initial Release.
Quartus II
Updated
Updated
Minor text edit.
Updated Table 3–1.
Updated “Byte Enable Support”, “Simple Dual-Port Mode”, and
“Read and Write Clock Mode” sections.
Updated Figure 3–1, Figure 3–2, Figure 3–5, Figure 3–9,
Figure 3–12, Figure 3–18, Figure 3–19, and Figure 3–20.
Added Figure 3–2, Figure 3–6, Figure 3–10, and Figure 3–13.
lists the revision history for this chapter.
Table
Figure
Handbook.
3–2.
3–14.
Changes Made
RAM Megafunction User Guide
Arria II GX Device Handbook, Volume 1
Updated for Arria II GX
v9.1 release.
Summary of Changes
and
3–19

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