EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 172

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–14
Arria II GX External Memory Interface Features
Arria II GX Device Handbook, Volume 1
f
1
Table 7–3
a ×32/×36 group on Arria II GX devices lacking a native ×32/×36 DQ/DQS group.
Table 7–3. Possible Group Combinations in Arria II GX Devices
Arria II GX devices are rich with features that allow robust high-performance external
memory interfacing. The Altera
interface features and helps set up the physical interface (PHY) best suited for your
system. This section describes each Arria II GX device feature that is used in external
memory interfaces from the DQS phase-shift circuitry and DQS logic block.
If you use the Altera memory controller MegaCore
megafunction and UniPHY IP core are instantiated for you.
For more information about supported external memory IPs, refer to
Section III: External Memory Interface System Specification
Memory Handbook.
358-Pin Ultra FineLine BGA
572-Pin FineLine BGA
780-Pin FineLine BGA
1152-Pin FineLine BGA
Notes to
(1) Only one ×8/×9 group left in each of the remaining I/O banks. You can form only 36 group write data with four
(2) This device supports 36 DQ/DQS groups on each side of I/O banks.
8/9 groups in these packages.
Table
lists the possible combinations to use two ×16/×18 DQ/DQS groups to form
Package
7–3:
(2)
(2)
Device Density
®
EP2AGX125
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGX45
EP2AGX65
EP2AGX45
EP2AGX65
EP2AGX95
EP2AGX45
EP2AGX65
EP2AGX95
EP2AGX95
Memory IPs allow you to use these external memory
Chapter 7: External Memory Interfaces in Arria II GX Devices
4A and 7A (Top and Bottom I/O banks)
7A and 8A (Top I/O banks)
5A and 6A (Right I/O banks)
3A and 4A (Bottom I/O banks)
7A and 8A (Top I/O banks)
5A and 6A (Right I/O banks)
3A and 4A (Bottom I/O banks)
7A and 8A (Top I/O banks)
5A and 6A (Right I/O banks)
3A and 4A (Bottom I/O banks)
Combine any two banks from each side of
I/O banks
®
Arria II GX External Memory Interface Features
functions, the ALTMEMPHY
in volume 1 of the External
I/O Bank Combinations
© July 2010 Altera Corporation
(1)