EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 194

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–10
Dynamic Phase Alignment (DPA) Block
Figure 8–7. DPA Clock Phase to Serial Data Timing Relationship
Note to
(1) T
Arria II GX Device Handbook, Volume 1
VCO
Figure
is defined as the PLL serial clock period.
8–7:
1
Dedicated SERDES and DPA circuitry only exist on the right side of the device. Top
and bottom I/O banks only support non-DPA mode, in which the SERDES are
implemented in the core logic.
The DPA block takes in high-speed serial data from the differential input buffer and
selects the optimal phase from one of the eight clock phases generated by the
center/corner PLL to sample the data. The eight phases of the clock are equally
divided, giving a 45° resolution. The maximum phase offset between the received
data and the selected phase is 1/8 unit interval (UI), which is the maximum
quantization error of the DPA. The optimal clock phase selected by the DPA block
(DPA_diffioclk) is also used to write data into the FIFO buffer or to clock the
SERDES for soft-CDR operation.
between the DPA clocks and the incoming serial data.
The DPA block requires a training pattern and a training sequence of at least 256
repetitions. The training pattern is not fixed, so you can use any training pattern with
at least one transition. An optional user controlled signal (rx_dpll_hold) freezes
the DPA on its current phase when asserted. This is useful if you do not want the DPA
to continuously adjust phase after initial phase selection.
The DPA loses lock when it switches phases to maintain an optimal sampling phase.
After it is locked, the DPA can lose lock under either of the following conditions:
■
■
An independent reset signal (rx_reset) is routed from the FPGA fabric to reset the
DPA circuitry in user mode. The DPA circuitry must be retrained after reset.
rx_in
135˚
180˚
225˚
270˚
315˚
45˚
90˚
0˚
One phase change (adjacent to the current phase)
Two phase changes in the same direction
0.125T
D0
vco
D1
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
T
D2
vco
Figure 8–7
(Note 1)
D3
shows the possible phase relationships
D4
Dn
© July 2010 Altera Corporation
Differential Receiver