EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 167

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Arria II GX Devices
Arria II GX Memory Interfaces Pin Support
Figure 7–7. Number of DQ/DQS Groups per Bank in EP2AGX95, EP2AGX125, EP2AGX190 and EP2AGX260 Devices in the
780-Pin FineLine BGA Package
Notes to
(1) All I/O pin counts include 12 dedicated clock inputs (CLK4 to CLK15) that you can use for data inputs.
(2) Several configuration pins in Bank 6A are shared with DQ/DQS pins. You cannot use a 4 DQ/DQS group with any of its pin members used for
© July 2010 Altera Corporation
configuration purposes. Ensure that the DQ/DQS groups you have chosen are not also used for configuration.
Figure
7–7:
Figure 7–7
EP2AGX125, EP2AGX190, and EP2AGX260 devices in the 780-pin FineLine BGA
package.
(Note
shows the number of DQ/DQS groups per bank in Arria II GX EP2AGX95,
EP2AGX95, EP2AGX125, EP2AGX190,
58 User I/Os
I/O Bank 8A
×16/×18=1
×32/×36=0
54 User I/Os
×16/×18=1
×32/×36=0
I/O Bank 3A
×8/×9=3
×8/×9=3
1),
×4=6
×4=6
in the 780-Pin FineLine BGA
and EP2AGX260 Devices
(2)
70 User I/Os
I/O Bank 4A
74 User I/Os
I/O Bank 7A
×16/×18=2
×32/×36=1
×16/×18=2
×32/×36=1
×8/×9=4
×8/×9=4
×4=8
×4=8
66 User I/Os
I/O Bank 6A
50 User I/Os
×16/×18=1
×32/×36=0
I/O Bank 5A
×16/×18=2
×32/×36=1
×8/×9=3
×8/×9=4
×4=6
×4=8
Arria II GX Device Handbook, Volume 1
7–9