EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 247

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Passive Serial Configuration
Figure 9–14. PS Configuration Using a USB-Blaster, EthernetBlaster, MasterBlaster, ByteBlaster II, or ByteBlasterMV Cable
Notes to
(1) Connect the pull-up resistor to the same supply voltage (V
(2) You only need the pull-up resistors on DATA0 and DCLK if the download cable is the only configuration scheme used on your board. This ensures
(3) In the ByteBlasterMV cable, pin 6 is a no connect. In the USB-Blaster and ByteBlaster II cables, this pin is connected to nCE when it is used for
(4) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL[3..0], refer to
© July 2010
that DATA0 and DCLK are not left floating after configuration. For example, if you are also using a configuration device, you do not need the
pull-up resistors on DATA0 and DCLK.
AS programming; otherwise, it is a no connect.
Figure
Altera Corporation
V
CCIO
9–14:
10 kΩ
(1)
(2)
V
10 kΩ
CCIO
(2)
Figure 9–14
ByteBlaster II, ByteBlasterMV, or Ethernet Blaster cable.
You can use a download cable to configure multiple Arria II GX devices by connecting
the nCEO pin of each device to the nCE pin of the subsequent device. The nCE pin of
the first device is connected to GND, while its nCEO pin is connected to the nCE of the
next device in the chain. The nCE input of the last device comes from the previous
device, while its nCEO pin is left floating. All other configuration pins (nCONFIG,
nSTATUS, DCLK, DATA0, and CONF_DONE) are connected to every device in the chain.
Because all CONF_DONE pins are tied together, all devices in the chain initialize and
enter user mode at the same time.
In addition, because the nSTATUS pins are tied together, the entire chain halts
configuration if any device detects an error. The Auto-restart configuration after
error option does not affect the configuration cycle because you must manually restart
configuration in the Quartus II software when an error occurs.
(1)
V
CCIO
10 kΩ
(1)
shows PS configuration for Arria II GX devices using a USB-Blaster,
GND
(4)
CCIO
nCE
DCLK
DATA0
nCONFIG
MSEL[3..0]
Arria II GX Device
) as the USB-Blaster, ByteBlaster II, ByteBlasterMV, or EthernetBlaster cable.
CONF_DONE
nSTATUS
nCEO
N.C.
V
CCIO
10 kΩ
(1)
V
CCIO
10 kΩ
(1)
Pin 1
Arria II GX Device Handbook, Volume 1
10-Pin Male Header
Download Cable
(PS Mode)
Shield
GND
V
V
CCIO
IO
(3)
GND
(1)
Table
9–2.
9–27