EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 249

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
JTAG Configuration
JTAG Configuration
Table 9–8. Dedicated JTAG Pins (Part 1 of 2)
© July 2010
TDI
TDO
Name
Pin
Altera Corporation
f
f
Test data
Test data
1
1
output
Pin Type
input
The JTAG has developed a specification for boundary-scan testing. This
boundary-scan test (BST) architecture offers the capability to efficiently test
components on PCBs with tight lead spacing. The BST architecture can test pin
connections without using physical test probes and capture functional data while a
device is operating normally. You can also use JTAG circuitry to shift configuration
data into the device. The Quartus II software automatically generates .sof that you
can use for JTAG configuration with a download cable in the Quartus II software
programmer.
For more information about JTAG boundary-scan testing and commands available
using Arria II GX devices, refer to the following documents:
■
■
Arria II GX devices are designed such that JTAG instructions have precedence over
any device configuration modes. Therefore, JTAG configuration can take place
without waiting for other configuration modes to complete. For example, if you
attempt JTAG configuration of Arria II GX devices during PS configuration, PS
configuration is terminated and JTAG configuration begins.
You cannot use the Arria II GX decompression or design security features if you are
configuring your Arria II GX device using JTAG-based configuration.
A device operating in JTAG mode uses four required pins, TDI, TDO, TMS, and TCK.
The TCK pin has an internal weak pull-down resistor, while the TDI and TMS pins
have weak internal pull-up resistors (typically 25 k ). All the JTAG pins are powered
by the V
I/O standard.
All user I/O pins are tri-stated during JTAG configuration.
of each JTAG pin.
For recommendations about how to connect a JTAG chain with multiple voltages
across the devices in the chain, refer to the
JTAG Boundary Scan Testing
Programming Support for Jam STAPL Language
CCIO
Serial input pin for instructions as well as test and programming data. Data is shifted in on
the rising edge of TCK. If the JTAG interface is not required on the board, you can disable
the JTAG circuitry by connecting this pin to logic high.
Serial data output pin for instructions as well as test and programming data. Data is
shifted out on the falling edge of TCK. The pin is tri-stated if data is not being shifted out
of the device. If the JTAG interface is not required on the board, you can disable the JTAG
circuitry by leaving this pin unconnected.
power supply of I/O bank 8C. All the JTAG pins support only the LVTTL
chapter
Description
JTAG Boundary Scan Testing
Arria II GX Device Handbook, Volume 1
Table 9–8
lists the function
chapter.
9–29