EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 245

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Passive Serial Configuration
Figure 9–13. PS Configuration Timing Waveform
Notes to
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels.
(2) After power up, the Arria II GX device holds nSTATUS low for the time of the POR delay.
(3) After power up, before and during configuration, CONF_DONE is low.
(4) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(5) DATA[0]is a dedicated pin that is used for both passive and active configuration modes and is not available as a user I/O pin after configuration.
(6) Two DCLK falling edges are required after CONF_DONE goes high to begin initialization of the device.
Table 9–7. PS Timing Parameters for Arria II GX Devices (Part 1 of 2)—Preliminary
© July 2010
t
t
t
t
t
t
t
t
t
t
t
t
f
CF2CD
CF2ST0
CFG
STATUS
CF2ST1
CF2CK
ST2CK
DSU
DH
CH
CL
CLK
MAX
Symbol
When nCONFIG is pulled low, a reconfiguration cycle begins.
Figure
Altera Corporation
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
nCONFIG low pulse width
nSTATUS low pulse width
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
Data setup time before rising edge on DCLK
Data hold time after rising edge on DCLK
DCLK high time
DCLK low time
DCLK period
DCLK frequency
9–13:
CONF_DONE (3)
nSTATUS (2)
INIT_DONE
nCONFIG
PS Configuration Timing
Figure 9–13
device or microprocessor as an external host.
Table 9–7
User I/O
DCLK
DATA
t
t
lists the timing parameters for Arria II GX devices for PS configuration.
CFG
CF2CD
Parameter
shows the timing waveform for PS configuration when using a MAX II
t
CF2ST1
t
CF2ST0
t
CF2CK
t
ST2CK
t
Bit 0 Bit 1 Bit 2 Bit 3
STATUS
High-Z
t
CH
t
CLK
t
DSU
t
CL
t
DH
(Note 1)
Bit n
(6)
Minimum
500
3.2
3.2
—
—
10
—
—
2
2
4
0
8
t
CD2UM
Arria II GX Device Handbook, Volume 1
Maximum
800
500
800
500
125
—
—
—
—
—
—
—
—
User Mode
(5)
(4)
(1)
(1)
Units
MHz
s
s
s
s
s
ns
ns
ns
ns
ns
ns
ns
9–25