EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 121

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II GX Devices
PLLs in Arria II GX Devices
Figure 5–22. Manual Clock Switchover Circuitry in Arria II GX PLLs
© July 2010
Altera Corporation
f
clkswitch
inclk0
inclk1
Figure 5–22
For more information about PLL software support in the Quartus II software, refer to
the
Clock Switchover Guidelines
Use the following guidelines when implementing clock switchover in Arria II GX
PLLs.
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■
■
■
■
■
Automatic clock switchover requires that the inclk0 and inclk1 frequencies be
in 100% (2×) of each other. Failing to meet this requirement causes the clkbad[0]
and clkbad[1] signals to not function properly.
When you use manual clock switchover mode, the difference between inclk0
and inclk1 can be more than 100% (2×). However, differences in frequency, or
phase of the two clock sources, or both, are likely to cause the PLL to lose lock.
Resetting the PLL ensures that the correct phase relationships are maintained
between the input and output clocks.
1
Applications that require a clock switchover feature and a small frequency drift
must use a low-bandwidth PLL. The low-bandwidth PLL reacts more slowly than
the high-bandwidth PLL to reference the input clock changes. When the
switchover event occurs, a low-bandwidth PLL propagates the stopping of the
clock to the output more slowly than the high-bandwidth PLL. However, be aware
that the low-bandwidth PLL also increases lock time.
After a switchover event occurs, there may be a finite resynchronization period for
the PLL to lock onto a new clock. The exact amount of time it takes for the PLL to
relock depends on the PLL configuration.
If the phase relationship between the input clock to the PLL and the output clock
from the PLL is important in your design, assert areset for at least 10 ns after
performing a clock switchover.
To prevent clock glitches from propagating through your design during PLL
resynchronization or after areset is applied, use the clock enable feature of the
clock control block to disable the clock network. Wait for the locked signal to assert
and become stable before reenabling the output clocks from the PLL at the clock
control block.
Phase-Locked Loops (ALTPLL) Megafunction User
Control Logic
Clock Switch
Both inclk0 and inclk1 must be running when the clkswitch signal
goes high to start the manual clock switchover event. Failing to meet this
requirement causes the clock switchover to not function properly.
shows a block diagram of the manual switchover circuit.
muxout
n Counter
refclk
Guide.
PFD
Arria II GX Device Handbook, Volume 1
fbclk
5–29