EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 56

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–16
Read and Write Clock Mode
Single Clock Mode
Design Considerations
Memory Block Selection
Conflict Resolution
Arria II GX Device Handbook, Volume 1
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Arria II GX memory blocks can implement read and write clock mode for simple
dual-port memories. In this mode, a write clock controls the data-input,
write-address, and write-enable registers. Similarly, a read clock controls the
data-output, read-address, and read-enable registers. The memory blocks support
independent clock enables for both the read and write clocks. Asynchronous clears
are available on data output latches and registers only.
If you perform a simultaneous read and write to the same address location when
using read and write clock mode, the output read data will be unknown. If you
require the output data to be a known value, use either single clock mode or input and
output clock mode, and choose the appropriate read-during-write behavior in the
MegaWizard Plug-In Manager.
Arria II GX memory blocks can implement single-clock mode for true dual-port,
simple dual-port, and single-port memories. In this mode, a single clock, together
with a clock enable, is used to control all registers of the memory block.
Asynchronous clears are available on output latches and output registers only.
This section describes guidelines for designing with memory blocks.
The Quartus II software automatically partitions user-defined memory into
embedded memory blocks by taking into account both speed and size constraints
placed on your design. For example, the Quartus II software may spread out memory
across multiple memory blocks when resources are available to increase the
performance of your design. You can manually assign memory to a specific block size
using the RAM MegaWizard Plug-In Manager.
MLABs can implement single-port SRAM through emulation with the Quartus II
software. Emulation results in minimal additional logic resources used. Because of the
dual-purpose architecture of the MLAB, it only has data input registers and output
registers in the block. MLABs gain input address registers and additional optional
data output registers from adjacent ALMs with register packing.
For more information about register packing, refer to the
Adaptive Logic Modules in Arria II GX Devices
When using the memory blocks in true dual-port mode, it is possible to attempt two
write operations to the same memory location (address). Because there is no conflict
resolution circuitry built into the memory blocks, this results in unknown data being
written to that location. Therefore, you must implement conflict resolution logic,
external to the memory block, to avoid address conflicts.
chapter.
Chapter 3: Memory Blocks in Arria II GX Devices
Logic Array Blocks and
© November 2009 Altera Corporation
Design Considerations