EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 66

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–6
Table 4–2. Arria II GX DSP Block Operational Modes (Part 2 of 2)
DSP Block Resource Descriptions
Arria II GX Device Handbook, Volume 1
Notes to
(1) This mode also supports loopback mode. In loopback mode, the number of loopback multipliers per DSP block is two. You can use the remaining
(2) Unsigned value is also supported, but you must ensure that the result can be contained in 36 bits.
(3) Dynamic shift mode supports arithmetic shift left, arithmetic shift right, logical shift left, logical shift right, and rotation operation.
(4) Dynamic shift mode operates on a 32-bit input vector, but the multiplier width is configured as 36 bits.
Multiplier Adder
High Precision
Shift
multipliers in regular two-multiplier adder mode.
Mode
Table
(3)
4–2:
Multiplier
in Width
36-bits
18x36
(4)
The DSP block consists of two identical halves: top-half and bottom-half. Each half
has four 18 × 18 multipliers.
Arria II GX DSP blocks can operate in different modes simultaneously. Each half block
is fully independent except for the sharing of the four clock, ena, and the aclr
signals. For example, you can break down a single DSP block to operate a 9 × 9
multiplier in one half block and an 18 × 18 two-multiplier adder in the other half
block. This increases DSP block resource efficiency and allows you to implement more
multipliers in an Arria II GX device. The Quartus
multipliers that can share the same DSP block resources in the same block.
The DSP block consists of the following elements:
■
■
■
■
■
■
Input register bank
Four two-multiplier adders
Pipeline register bank
Four second-stage adders
Four round and saturation logic units
Second adder register and output register bank
Number of
Multiplier
1
2
Block
# per
2
2
Signed or
Unsigned
Both
Both
RND,
SAT
No
No
Register
®
In Shift
II software automatically places
No
No
Chapter 4: DSP Blocks in Arria II GX Devices
Chainout
Adder
DSP Block Resource Descriptions
No
© July 2010 Altera Corporation
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1st Stage
Add/Sub
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2nd Stage
Add Only
Add/Acc
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