EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 93

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Clock Networks in Arria II GX Devices
Table 5–1. Clock Resources in Arria II GX Devices
© July 2010
AIIGX51005-3.0
Clock input pins
GCLK networks
RCLK networks
PCLK networks
GCLKs/RCLKs per quadrant
GCLKs/RCLKs per device
Note to
(1) There are 50 PCLKs in EP2AGX45 and EP2AGX65 devices, where 18 are on the left side and 32 on the right side. There are 59 PCLKs in
EP2AGX95 and EP2AGX125 device, where 27 are on the left side and 32 on the right side. There are 84 PCLKS in EP2AGX190 and EP2AGX260
devices, where 36 are on the left side and 48 on the right side.
Clock Resource
Table
Altera Corporation
5–1:
Arria
loops (PLLs) with advanced features. Arria II GX devices provide dedicated global
clock networks (GCLKs), regional clock networks (RCLKs), and periphery clock
networks (PCLKs).
This chapter contains the following sections:
■
■
The GCLKs, RCLKs, and PCLKs available in Arria II GX devices are organized into
hierarchical clock structures that provide up to 148 unique clock domains
(16 GCLK + 48 RCLK + 84 PCLK) and allow up to 52 unique GCLK, RCLK, and PCLK
clock sources (16 GCLK + 12 RCLK + 24 PCLK) per device quadrant.
the clock resources available in Arria II GX devices.
Arria II GX devices have up to 12 dedicated single-ended clock pins or six dedicated
differential clock pins (DIFFCLK_[0..5]p and DIFFCLK_[0..5]n) that can drive
either the GCLK or RCLK networks. These clock pins are arranged on the three sides
(top, bottom, and right sides) of the Arria II GX device, as shown in
Figure
“Clock Networks in Arria II GX Devices”
“PLLs in Arria II GX Devices” on page 5–13
®
II GX devices provide a hierarchical clock structure and multiple phase-locked
5–2.
Number of Resources Available
84 (24 per device quadrant)
12 Single-ended
(6 Differential)
5. Clock Networks and PLLs in Arria II GX
16
48
28
64
(1)
CLK[4..15]
CLK[4..15] pins, PLL clock outputs,
programmable logic device (PLD)-transceiver
interface clocks, and logic array
CLK[4..15] pins, PLL clock outputs,
PLD-transceiver interface clocks, and logic array
Dynamic phase alignment (DPA) clock outputs,
PLD-transceiver interface clocks, horizontal I/O
pins, and logic array
16 GCLKs + 12 RCLKs
16 GCLKs + 48 RCLKs
Source of Clock Resource
, DIFFCLK_[0..5]p/n pins
Arria II GX Device Handbook, Volume 1
Figure 5–1
Table 5–1
Devices
lists
and