EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 175

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Arria II GX Devices
Arria II GX External Memory Interface Features
© July 2010 Altera Corporation
1
1
1
DLL
DQS phase-shift circuitry uses a DLL to dynamically control the clock delay needed
by the DQS/CQ and CQn pins. The DLL, in turn, uses a frequency reference to
dynamically generate control signals for the delay chains in each of the DQS/CQ and
CQn pins, allowing it to compensate for PVT variations. The DQS delay settings are
Gray-coded to reduce jitter when the DLL updates the settings. Phase-shift circuitry
requires a maximum of 1,280 clock cycles to lock and calculate the correct input clock
period when the DLL is in low jitter mode. Otherwise, only 256 clock cycles are
required. Do not send data during these clock cycles because there is no guarantee
that the data is properly captured. As the settings from the DLL may not be stable
until this lock period has elapsed, be aware that anything with these settings may be
unstable during this period.
You can still use the DQS phase-shift circuitry for any memory interfaces that are
operating at less than 100 MHz. However, the DQS signal may not shift over 2.5 ns. At
less than 100 MHz, while the DQS phase shift may not be exactly centered to the data
valid window, sufficient margin needs to still exist for reliable operation.
There are two DLLs in an Arria II GX device, located in the top-left and bottom-right
corners of the device. These two DLLs can support a maximum of two unique
frequencies, with each DLL running at one frequency. Each DLL can have two outputs
with different phase offsets, which allows one Arria II GX device to have four
different DLL phase-shift settings.
Each DLL can access the top, bottom, and right side of the device. This means that
each I/O bank is accessible by two DLLs, giving more flexibility to create multiple
frequencies and multiple-type interfaces. The DLL outputs the same DQS delay
settings for the different sides of the device.
Interfaces that span across two sides of the device are not recommended for
high-performance memory interface applications. However, Arria II GX devices
support split interfaces (top and bottom I/O banks) and interfaces with multiple
DQ/DQS groups wrapping over column and row I/Os from adjacent sides of the
devices. Interfaces spanning “top and bottom I/O banks”, “right and bottom I/O
banks”, or “top, bottom, and right I/O banks” are supported.
Each bank can use settings from either one or both DLLs. For example, DQS1R can get
its phase-shift settings from DLL0, and DQS2R can get its phase-shift settings from
DLL1.
The reference clock for each DLL might come from PLL output clocks or dedicated
clock input pins, as specified in
If you have a dedicated PLL that only generates the DLL input reference clock, set the
PLL mode to No Compensation or the Quartus II software automatically changes it.
Because the PLL does not use any other outputs, it does not have to compensate for
any clock paths.
Table
7–4.
Arria II GX Device Handbook, Volume 1
7–17