EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 143

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 6: I/O Features in Arria II GX Devices
Arria II GX I/O Structure
Programmable Slew Rate Control
Open-Drain Output
Bus Hold
© July 2010 Altera Corporation
1
The output buffer for each Arria II GX device regular- and dual-function I/O pin has a
programmable output slew rate control that you can configure for low-noise or
high-speed performance. A faster slew rate provides high-speed transitions for
high-performance systems. A slow slew rate can help reduce system noise, but adds a
nominal delay to the rising and falling edges. Each I/O pin has an individual slew
rate control, allowing you to specify the slew rate on a pin-by-pin basis.
You cannot use the programmable slew rate feature with R
The Quartus
control. In the Quartus II Assignment Editor, setting 1 = fast, and 0 = slow.
Programmable slew rate is available for 8 mA current strength and above for
non-voltage referenced I/O standards except for 3.3-V LVTTL/LVCMOS.
You can use faster slew rates to improve the available timing margin in
memory-interface applications or when the output pin has high-capacitive loading.
Altera recommends performing IBIS or SPICE simulations to determine the right slew
rate setting for your specific application.
Arria II GX devices provide an optional open-drain output (equivalent to an open
collector output) for each I/O pin. When configured as open drain, the logic value of
the output is either high-Z or 0. You must use an external pull-up resistor to pull the
high-Z output to logic high.
Each Arria II GX device I/O pin provides an optional bus-hold feature. Bus-hold
circuitry can weakly hold the signal on an I/O pin at its last-driven state. Because the
bus-hold feature holds the last-driven state of the pin until the next input signal is
present, an external pull-up or pull-down resistor is not required to hold a signal level
when the bus is tri-stated.
Bus-hold circuitry also pulls non-driven pins away from the input threshold voltage
where noise can cause unintended high-frequency switching. You can select this
feature individually for each I/O pin. The bus-hold output drives no higher than V
to prevent over-driving signals. If you enable the bus-hold feature, you cannot use the
programmable pull-up option. The bus-hold feature is disabled if the I/O pin is
configured for differential signals.
Bus-hold circuitry uses a resistor with a nominal resistance to weakly pull the
last-driven state.
Bus-hold circuitry is active only after configuration. When going into user mode, the
bus-hold circuit captures the value on the pin present at the end of configuration.
®
II software allows fast and slow settings for programmable slew rate
Arria II GX Device Handbook, Volume 1
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OCT.
CCIO
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