EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 203

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
LVDS and DPA Clock Networks
LVDS and DPA Clock Networks
Figure 8–16. LVDS and DPA Clock Networks in the Arria II GX Devices without Center PLLs
Figure 8–17. LVDS and DPA Clock Networks in the Arria II GX Devices with Center PLLs
© July 2010
Altera Corporation
f
clock networks on the
clock networks on the
left side of the device
left side of the device
No LVDS and DPA
No LVDS and DPA
For more information about PLLs, refer to the
Devices
The Arria II GX devices only have LVDS and DPA clock networks on the right side of
the device. The center/corner PLLs feed into the differential transmitter and receiver
channels through the LVDS and DPA clock networks.
show the LVDS clock tree for family members without center PLLs and with center
PLLs, respectively. The center PLLs can drive the LVDS clock tree above and below
them. In Arria II GX devices with or without center PLLs, the corner PLLs can drive
both top and bottom LVDS clock tree.
chapter.
Quadrant
Quadrant
Quadrant
Quadrant
Quadrant
Quadrant
Quadrant
Quadrant
Clock Network and PLLs in Arria II GX
Clock
Clock
DPA
DPA
Clock
DPA
Corner
Center
Center
Corner
PLL
PLL
PLL
PLL
Corner
Corner
PLL
PLL
LVDS
LVDS
Clock
Clock
Figure 8–16
LVDS
Clock
Arria II GX Device Handbook, Volume 1
4
4
8
8
4
4
4
8
4
4
4
4
4
and
Figure 8–17
8–19