EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 129

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II GX Devices
PLLs in Arria II GX Devices
Table 5–15. Dynamic Phase-Shifting Control Signals (Part 2 of 2)
© July 2010
SCANCLK
PHASEDONE
Signal Name
Altera Corporation
1
Free running clock from core used in
combination with PHASESTEP to enable,
disable, or both dynamic phase shifting. Shared
with scanclk for dynamic reconfiguration.
When asserted, this indicates to the core logic
that the phase adjustment is complete and the
PLL is ready to act on a possible second
adjustment pulse. Asserts based on internal
PLL timing. Deasserts on the rising edge of
scanclk.
Table 5–16
PHASECOUNTERSELECT setting.
Table 5–16. Phase Counter Select Mapping
To perform one dynamic phase-shift, follow these steps:
1. Set phaseupdown and phasecounterselect as required.
2. Assert phasestep for at least two scanclk cycles. Each phasestep pulse
3. Deassert phasestep.
4. Wait for phasedone to go high.
5. Repeat steps
All signals are synchronous to scanclk and must meet the t
with respect to the scanclk edges. They are latched on scanclk edges and must
meet the t
You can repeat dynamic phase-shifting indefinitely. For example, in a design where
the VCO frequency is set to 1,000 MHz and the output clock frequency is set to
100 Mhz, performing 40 dynamic phase shifts (each one yields 125 ps phase shift)
results in shifting the output clock by 180°, in other words, a phase shift of 5 ns.
allows one phase shift.
phase-shifts.
PHASECOUNTERSELECT[3]
su
lists the PLL counter selection based on the corresponding
and t
Description
0
0
0
0
0
0
0
0
1
1
h
through
requirements with respect to the scanclk edges.
4
as many times as required to perform multiple
[2]
0
0
0
0
1
1
1
1
0
GCLK, RCLK, or
I/O pin
PLL reconfiguration
circuit
[1]
0
0
1
1
0
0
1
1
0
Source
[0]
0
1
0
1
0
1
0
1
0
Arria II GX Device Handbook, Volume 1
su
PLL reconfiguration circuit
Logic array or I/O pins
and t
All Output Counters
C0 Counter
C1 Counter
C2 Counter
C3 Counter
C4 Counter
C5 Counter
C6 Counter
h
M Counter
Destination
Selects
requirements
5–37