EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 64

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–4
Arria II GX Device Handbook, Volume 1
Equation 4–3. Four-Multiplier Adder Equation (44-Bit Accumulation)
In these equations, n denotes sample time and P[36..0] are the results from the
two-multiplier adder units.
Equation 4–2
(four-multiplier adder), and
operation, but with a maximum of a 44-bit accumulation capability by feeding the
output from the output register bank back to the adder/accumulator block. For the
output register bank and adder/accumulator block, refer to
You can bypass all register stages depending on which mode you select.
To support finite impulse response (FIR)-like structures efficiently, a major addition to
the DSP block in Arria II GX devices is the ability to propagate the result of one half
block to the next half block completely in the DSP block without additional soft logic
overhead. This is achieved by the inclusion of a dedicated addition unit and routing
that adds the 44-bit result of a previous half block with the 44-bit result of the current
block. The 44-bit result is either fed to the next half block or out of the DSP block using
the output register stage, as shown in
later sections.
To support single-channel type FIR filters efficiently, you can configure one of the
multiplier input’s registers to form a tap delay line input, saving resources and
providing higher system performance.
provides a sum of four 18 × 18-bit multiplication operations
W
n
Equation 4–3
[43..0] = W
Figure
n-1
provides a four 18 × 18-bit multiplication
[43..0] ± Z
4–3. Detailed examples are described in
Chapter 4: DSP Blocks in Arria II GX Devices
n
[37..0]
Figure
© July 2010 Altera Corporation
4–3.
Simplified DSP Operation