EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 252

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–32
Figure 9–17. JTAG Configuration of Multiple Devices Using a Download Cable
Notes to
(1) Connect the pull-up resistors to the V
(2) You must connect the pull-up resistor to the same supply voltage as the USB-Blaster, ByteBlaster II, ByteBlasterMV, or EthernetBlaster cable. You
(3) In the USB-Blaster, ByteBlaster II, and ByteBlasterMV cables, pin 6 is a no connect.
(4) You must connect nCE to GND or drive it low for successful JTAG configuration.
(5) You must connect the nCONFIG and MSEL[3..0] pins to support a non-JTAG configuration scheme. If you only use JTAG configuration,
(6) Resistor value can vary from 1 K
Arria II GX Device Handbook, Volume 1
Pin 1
can connect the voltage supply to the V
connect nCONFIG to the V
whichever is convenient on your board.
10-Pin Male Header
Download Cable
(JTAG Mode)
Figure
V
CCIO
9–17:
(2)
V
(3)
IO
1 kΩ
(6)
V
CCIO
V
CCIO
(2)
Table 9–9. Dedicated Configuration Pin Connections During JTAG Configuration (Part 2 of 2)
When programming a JTAG device chain, one JTAG-compatible header is connected
to several devices. The number of devices in the JTAG chain is limited only by the
drive capability of the download cable. When four or more devices are connected in a
JTAG chain, Altera recommends buffering the TCK, TDI, and TMS pins with an
on-board buffer.
JTAG-chain device programming is ideal when the system contains multiple devices
or when testing your system using JTAG BST circuitry.
Figure 9–17
(6)
(2)
CONF_DONE
DCLK
CCIO
Signal
power supply of the bank in which the pin resides and MSEL[3..0] to GND. Pull DCLK either high or low,

(5)
(5)
(5)
V
CCIO (1)
to 10 K
CCIO
10 kΩ
CCIO
TDI
nSTATUS
nCONFIG
DCLK
MSEL[3..0]
nCE
shows a multi-device JTAG configuration.
power supply of I/O bank 3C.
TMS
Arria II GX Device

power supply of I/O bank 8C of the device.
(4)
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
.
Pull to the V
resistor. When configuring multiple devices in the same JTAG chain, each
CONF_DONE pin must be pulled up to the V
which the pin resides individually. CONF_DONE going high at the end of JTAG
configuration indicates successful configuration.
Do not leave floating. Drive low or high, whichever is more convenient on your
board.
CONF_DONE
TCK
TDO
V
CCIO
CCIO (1)
10 kΩ
power supply of the bank in which the pin resides using a 10-
(5)
(5)
(5)
V
CCIO (1)
10 kΩ
TDI
nSTATUS
nCONFIG
DCLK
MSEL[3..0]
nCE
TMS
Arria II GX Device
(4)
CONF_DONE
TCK
Description
TDO
V
CCIO (1)
10 kΩ
CCIO
(5)
(5)
(5)
V
CCIO (1)
power supply of the bank in
10 kΩ
TDI
nSTATUS
nCONFIG
DCLK
MSEL[3..0]
nCE
Stratix II or Stratix II GX
TMS
Arria II GX Device
© July 2010 Altera Corporation
(4)
Device
CONF_DONE
TCK
TDO
JTAG Configuration
V
CCIO (1)
10 kΩ
k