EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 223

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Power-On Reset Circuit and Configuration Pins Power Supply
Power-On Reset Circuit and Configuration Pins Power Supply
Power-On Reset Circuit
V
© July 2010
CCIO
Pins for I/O Banks 3C and 8C
Altera Corporation
You can also refer to the following:
■
■
■
■
If your system already contains a common flash interface flash memory device, you
can also use it for the Arria II GX device configuration storage. The Parallel Flash
Loader feature in MAX II devices provides an efficient method to program common
flash interface flash memory devices through the JTAG interface and logic to control
configuration from the flash memory device to the Arria II GX device. Both PS and
FPP configuration modes are supported using the Parallel Flash Loader feature.
For more information about programming Altera serial configuration devices, refer to
“Programming Serial Configuration Devices” on page
The following section describes the power-on reset (POR) circuit and the power
supply for the configuration pins.
The POR circuit keeps the entire system in reset mode until the power supply voltage
levels have stabilized on power up. After power up, the device does not release
nSTATUS until V
the POR trip point of the device. On power down, brown-out occurs if the V
down below the POR trip point and any of the V
8C drops below the threshold level of the hot-socket circuitry.
In Arria II GX devices, you can select between a fast POR time or a standard POR
time, depending on the MSEL pin settings. The fast POR time is 4 ms < T
for fast configuration time. The standard POR time 100 ms < T
a lower power-ramp rate.
In Arria II GX devices, all the dedicated configuration pins are supplied by the V
for I/O banks 3C and 8C in which they reside. The supported configuration voltages
are 1.8, 2.5, 3.0, and 3.3 V. Arria II GX devices do not support the 1.5-V configuration.
You must use V
inputs, dedicated configuration outputs, and dedicated configuration bidirectional
pins that you used for configuration. With V
configuration input buffers do not have to share power lines with the regular I/O
buffer.
For more information about the configuration data decompression feature, refer to
“Configuration Data Decompression” on page
For more information about the remote system upgrade feature, refer to
System Upgrades” on page
For more information about the design security feature, refer to the
Security” on page
For more information about the parallel flash loader, refer to
Megafunction User
CCIO
CCCB
for I/O banks 3C and 8C to power all dedicated configuration
, V
9–55.
Guide.
CCA_PLL
, V
9–43.
CC
, V
CCPD
, and V
CCIO
CCIO
for I/O banks 3C and 8C,
CC
, V
9–41.
for I/O banks 3C or 8C are above
CCPD
9–20.
, or V
Arria II GX Device Handbook, Volume 1
CCIO
POR
Parallel Flash Loader
< 300 ms, which has
for I/O banks 3C or
“Design
POR
“Remote
CC
< 12 ms
ramps
CCIO
9–3