EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 224

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–4
V
Configuration Process
Power Up
Arria II GX Device Handbook, Volume 1
CCPD
Pins
f
1
1
1
1
The operating voltage for the configuration input pin is independent of the I/O
bank’s V
configuration voltage constraints on V
You must power the dual function configuration pins that you used for configuration
with the V
information about configuration voltage standard applied to the V
refer to
For more information about the configuration pins connection recommendations,
refer to the
Arria II GX devices have a dedicated programming power supply (V
must connect to 3.3 V, 3.0 V, or 2.5 V to power the I/O pre-drivers, the HSTL/SSTL
input buffers, and the MSEL[3..0] pins.
V
voltage level in 100 ms (when you select standard POR time) or 4 ms (when you select
fast POR time). If these supplies are not ramped up in this specified time, your
Arria II GX device is not successfully configured.
You must connect V
■
■
■
For more information about configuration pins power supply, refer to
Configuration Pins” on page
The following sections describe the general configuration process for FPP, AS, and PS
schemes.
To begin the configuration process, you must fully power V
and V
reside) to the appropriate voltage levels.
For FPP configuration, pins DATA[7..1] are used and are supplied by the V
I/O bank 6A. You must power up this bank when you use the FPP configuration.
CCPD
For 3.3-V I/O standards, connect V
For 3.0-V I/O standards, connect V
For 2.5-V and below I/O standards, connect V
and V
CCIO
Table 9–2 on page
CCIO
(including I/O banks 3C and 8C where the configuration and JTAG pins
CCIO
Arria II GX Device Family Pin Connection
CCIO
power supply during configuration. Therefore, you do not require
power supply in which the configuration pins reside. For more
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
for I/O banks 3C and 8C must ramp up from 0 V to the desired
CCPD
according to the I/O standard used in the same bank:
9–7.
9–34.
CCIO
CCPD
CCPD
in Arria II GX devices.
to 3.3 V
to 3.0 V
CCPD
Guidelines.
to 2.5 V
CC
, V
© July 2010 Altera Corporation
CCCB
CCIO
, V
CCPD
Configuration Process
“Device
power supply,
CCA_PLL
) that you
, V
CCIO
CCPD
for
,