EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 287

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 10: SEU Mitigation in Arria II GX Devices
User Mode Error Detection
© July 2010
Altera Corporation
f
1
1
For more information about the timing requirement to shift out error information
from the error message register, refer to
The error detection logic continues to calculate the CRC_ERROR and 16-bit signatures
for the next frame of data, regardless of whether or not an error has occurred in the
current frame. You must monitor these signals and take the appropriate actions if a
soft error occurs.
The error detection circuitry in Arria II GX devices uses a 16-bit CRC-ANSI standard
(16-bit polynomial) as the CRC generator. The computed 16-bit CRC signature for
each frame is stored in the CRAM. The total storage size is 16 (number of bits per
frame) × the number of frames.
The Arria II GX device error detection CRC feature does not check memory blocks
and I/O buffers. Thus, the CRC_ERROR signal may stay solid high or low, depending
on the error status of the previously checked CRAM frame. The I/O buffers are not
verified during error detection because these bits use flipflops as storage elements
that are more resistant to soft errors compared to CRAM cells. MLAB and M9K
memory blocks support parity bits that are used to check the contents of memory
blocks for any error.
For more information about error detection in Arria II GX memory blocks, refer to the
Embedded Memory Blocks in Arria II GX Devices
To provide testing capability of the error detection block, a JTAG instruction,
EDERROR_INJECT, is provided. This instruction is able to change the content of the
21-bit JTAG fault injection register, used for error injection in Arria II GX devices,
thereby enabling testing of the error detection block.
You can only execute the EDERROR_INJECT JTAG instruction when the device is in
user mode.
Table 10–1
Table 10–1. EDERROR_INJECT JTAG Instruction
You can create a Jam™ file (.jam) to automate the testing and verification process.
This allows you to verify the CRC functionality in-system and on-the-fly, without
having to reconfigure the device.
You can introduce a single error or double errors adjacent to each other to the
configuration memory. This provides an extra way to facilitate design verification and
system fault tolerance characterization. Use the JTAG fault injection register with the
EDERROR_INJECT instruction to flip the readback bits. The Arria II GX device is then
forced into error test mode. Altera recommends reconfiguring the device after the test
completes.
EDERROR_INJECT
JTAG Instruction
lists the EDERROR_INJECT JTAG instruction.
Instruction Code
00 0001 0101
“Error Detection Timing” on page
This instruction controls the 21-bit JTAG fault
injection register, which is used for error
injection.
chapter.
Arria II GX Device Handbook, Volume 1
Description
10–7.
10–3