EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 179

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Arria II GX Devices
Arria II GX External Memory Interface Features
DQS Logic Block
Figure 7–13. Arria II GX DQS Logic Block
Notes to
(1) The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. For the exact PLL and input
(2) The dqsenable signal can also come from the Arria II GX FPGA fabric.
© July 2010 Altera Corporation
DQS phase-shift
settings from the
DQS phase-shift
clock pin, refer to
settings from
Phase offset
DQS delay
Figure
circuitry
circuitry
offsetctrlin [5:0]
f
delayctrlin [5:0]
7–13:
1
6
6
<dqs_offsetctrl_enable>
DQS/CQ or
0
1
CQn Pin
Table 7–4 on page 7–18
6
Bypass
If you use this feature, monitor the DQS delay settings to know how many offsets you
can add and subtract in the system. Note that the DQS delay settings output by the
DLL are also Gray-coded
For example, if the DLL determines that DQS delay settings of 28 are needed to
achieve a 30° phase shift in DLL frequency mode 1, you can subtract up to 28 phase
offset settings and you can add up to 35 phase offset settings to achieve the optimal
delay that you need. However, if the same DQS delay settings of 28 is needed to
achieve 30° phase shift in DLL frequency mode 4, you can still subtract up to 28 phase
offset settings, but you can only add up to 3 phase offset settings before the DQS delay
settings reach their maximum settings because DLL frequency mode 4 only uses 5-bit
DLL delay settings.
For more information about the value for each step, refer to the
Datasheet.
Each DQS/CQ and CQn pin is connected to a separate DQS logic block, which
consists of DQS delay chains, update enable circuitry, and DQS postamble circuitry
(refer
D
Input Reference
Q
dqsin
6
Clock (1)
Figure
0
1
6
DQS Delay Chain
D
7–13).
and
Q
dqsupdateen
Table 7–5 on page
6
0
1
6
<dqs_ctrl_latches_enable>
Circuitry
Update
Enable
7–20.
<phase_setting>
Resynchronization
Postamble
Enable
Clock
DQS Enable
dqsin
DQS Enable Control
dqsenablein
clk
dqsbusout
DQS bus
D
D
Arria II GX Device Handbook, Volume 1
Q
Q
dqsenable (2)
<delay_dqs_enable_by_half_cycle>
Arria II GX Device
Q
PRE
D
0
1
dqsenableout
7–21