EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 209

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
Differential Pin Placement Guidelines
Figure 8–22. Center PLLs Driving DPA-Enabled Differential I/Os
© July 2010
Altera Corporation
Using Both Center PLLs
You can use both center PLLs to drive DPA-enabled channels simultaneously, as long
as they drive these channels in their adjacent banks only, as shown in
If one of the center PLLs drives the DPA-enabled channels in the upper and lower I/O
banks, you cannot use the other center PLL for DPA, as shown in
If the upper center PLL drives DPA-enabled channels in the lower I/O bank, the
lower center PLL cannot drive DPA enabled channels in the upper I/O bank, and vice
versa. In other words, the center PLLs cannot drive cross-banks simultaneously, as
shown in
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
Reference
Reference
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Center
Center
CLK
CLK
PLL
PLL
Figure
8–23.
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
Reference
Reference
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Center
Diff I/O
Diff I/O
Center
CLK
CLK
PLL
PLL
Arria II GX Device Handbook, Volume 1
Figure
Unused
Figure
PLL
8–22.
8–21.
8–25