EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 233

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Fast Passive Parallel Configuration
Table 9–4. FPP Timing Parameters for Arria II GX Devices with Decompression and Design Security not Enabled
Figure 9–5. FPP Configuration Timing Waveform with Decompression or Design Security Enabled
Notes to
(1) Use this timing waveform when the decompression and/or design security features are used.
(2) The beginning of this waveform shows the device in user-mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic-high levels.
(3) After power up, the Arria II GX device holds nSTATUS low for the time of the POR delay.
(4) After power up, before and during configuration, CONF_DONE is low.
(5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(6) DATA[7..1] are available as user I/O pins after configuration. The state of these pins depends on the dual-purpose pin settings. DATA[0] is
(7) If required, you can pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[7..0] pins prior to
(8) Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the device.
© July 2010
CONF_DONE
t
t
t
t
Notes to
(1) Use these timing parameters when the decompression and design security features are not used.
(2) This value is obtainable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(3) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
(Note 1)
Symbol
CD2UM
CD2CU
CD2UMC
nSTATUS (3)
When nCONFIG is pulled low, a reconfiguration cycle begins.
a dedicated pin that is used for both the passive and active configuration modes and is not available as a user I/O pin after configuration.
sending the first DCLK rising edge.
Figure
INIT_DONE
Table
DATA[7..0]
(4)
nCONFIG
(Part 2 of 2)—Preliminary
User I/O
Input fall time
CONF_DONE high to user mode
CONF_DONE high to CLKUSR enabled
CONF_DONE high to user mode with CLKUSR option on
Altera Corporation
DCLK
9–5:
9–4:
t
t
CF2CD
CFG
Figure 9–5
device or microprocessor as an external host. This waveform shows timing when the
decompression and/or design security features are enabled.
t
CF2ST1
t
CF2ST0
t
CF2CK
t
ST2CK
t
STATUS
t
High-Z
DSU
1
Parameter
shows the timing waveform for FPP configuration when using a MAX II
2
Byte 0
t
DH
3
(3)
4
1
t
CH
2
Byte 1
t
CLK
t
t
CL
DH
3
4
(7)
t
4 × maximum
CD2CU
DCLK period
Minimum
CLKUSR
Byte 2
period)
1
+ (8532 ×
—
55
Byte (n-1)
3
Arria II GX Device Handbook, Volume 1
Maximum
(8)
4
150
40
—
—
Byte n
(Note
t
CD2UM
1),
(2)
(5)
(6)
Units
s
ns
—
—
User Mode
User Mode
9–13