EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 110

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–18
Arria II GX Device Handbook, Volume 1
Figure 5–12. Phase Relationship Between Clock and Data in Source-Synchronous Mode
Source-synchronous mode compensates for the delay of the clock network used plus
any difference in the delay between these two paths:
■
■
You can use the PLL Compensation assignment in the Quartus II software
Assignment Editor to select which input pins are used as the PLL compensation
targets. You can include your entire data bus, provided the input registers are clocked
by the same output of a source-synchronous compensated PLL. In order for the clock
delay to be properly compensated, all input pins must be on the same side of the
device. The PLL compensates for the input pin with the longest pad-to-register delay
among all input pins in the compensated bus.
If you do not assign the PLL Compensation assignment, the Quartus II software
automatically selects all pins driven by the compensated output of the PLL as the
compensation target.
Source-Synchronous Mode for LVDS Compensation
The goal of source-synchronous mode for LVDS compensation is to maintain the same
data and clock timing relationship seen at the pins at the internal
serializer/deserializer (SERDES) capture register, except that the clock is inverted
(180° phase shift), as shown in
the delay of the LVDS clock network plus any difference in the delay between these
two paths:
■
■
Data pin-to-IOE register input
Clock input pin-to-the PLL PFD input
Data pin-to-SERDES capture register
Clock input pin-to-SERDES capture register. In addition, the output counter must
provide the 180° phase shift.
Clock at register
reference clock
Data at register
at input pin
Data pin
PLL
Figure
5–13. Thus, this mode ideally compensates for
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
© July 2010 Altera Corporation
PLLs in Arria II GX Devices