EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 18

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–4
Table 1–3. Speed Grades for Arria II GX Devices
Arria II GX Device Architecture
Arria II GX Device Handbook, Volume 1
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGX45
EP2AGX65
EP2AGX95
Device
Arria II GX devices are available in up to four speed grades: –3 (fastest), –4, –5, and –6
(slowest).
Arria II GX devices include a customer-defined feature set optimized for
cost-sensitive applications and offer a wide range of density, memory, embedded
multiplier, I/O, and packaging options. Arria II GX devices support external memory
interfaces and I/O protocols required by wireless, wireline, broadcast, computer,
storage, and military markets. They inherit the 8-input ALM, M9K embedded RAM
block, and high-performance DSP blocks from the Stratix
cost-optimized I/O cell and a transceiver optimized for 6.375 Gbps speeds.
Figure 1–1
Figure 1–1. Arria II GX Device Architecture Overview
358-Pin Flip Chip
C4, C5, C6, I5
C4, C5, C6, I5
UBGA
—
—
—
—
Transceiver
PLL
Table 1–3
Blocks
shows an overview of the Arria II GX device architecture.
PLL
DLL
lists the speed grades for Arria II GX devices.
High-Speed Differential I/O,
General Purpose I/O, and
High-Speed Differential I/O,
General Purpose I/O, and
572-Pin Flip Chip
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
Plug and Play PCIe hard IP
×
Memory Interface
Memory Interface
1, × 4, and × 8
All the blocks in this graphic are for the largest density in the
Arria II GX family. The number of blocks can vary based on
FBGA
—
—
Embedded Memory, Clock Networks)
the density of the device.
(Logic Elements, DSP,
FPGA Fabric
780-Pin Flip Chip
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
High-Speed Differential I/O,
High-Speed Differential I/O,
General Purpose I/O, and
General Purpose I/O, and
Memory Interface
Memory Interface
FBGA
Chapter 1: Arria II GX Device Family Overview
®
IV device family with a
© July 2010 Altera Corporation
Arria II GX Device Architecture
1152-Pin Flip Chip
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
C4, C5, C6, I3, I5
Differential I/O
Differential I/O
High-Speed
High-Speed
DLL
Purpose
with DPA,
Interface
with DPA,
Purpose
General
I/O, and
Memory
Interface
General
I/O, and
Memory
PLL
PLL
PLL
FBGA
PLL
—
—