EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 177

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Arria II GX Devices
Arria II GX External Memory Interface Features
Figure 7–12. Simplified Diagram of the DQS Phase-Shift Circuitry
Notes to
(1) All features of the DQS phase-shift circuitry are accessible from the UniPHY IP core and ALTMEMPHY megafunction in the Quartus II software.
(2) The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. For the exact PLL and input
(3) Phase offset settings can only go to the DQS logic blocks.
(4) DQS delay settings can go to the logic array and DQS logic block.
© July 2010 Altera Corporation
clock pin, refer to
Input Reference
Figure
Clock (2)
7–12:
clk
DLL
Table 7–4
You can reset the DLL from either the logic array or a user I/O pin. Each time the DLL
is reset, you must wait for 1,280 clock cycles for the DLL to lock before you can
capture the data properly.
Depending on the DLL frequency mode, the DLL can shift the incoming DQS signals
by 0°, 22.5°, 30°, 36°, 45°, 60°, 67.5°, 72°, 90°, 108°, 120°, 135°, 144°, or 180°. The shifted
DQS signal is then used as the clock for the DQ IOE input registers.
All DQS/CQ and CQn pins, referenced to the same DLL, can have their input signal
phase shifted by a different degree amount but all must be referenced at one
particular frequency. For example, you can have a 90° phase shift on DQS1T and a 60°
phase shift on DQS2T, referenced from a 200-MHz clock. Not all phase-shift
combinations are supported. The phase shifts on the DQS pins referenced by the same
DLL must all be a multiple of 22.5° (up to 90°), 30° (up to 120°), 36° (up to 144°), or 45°
(up to 180°).
There are six different frequency modes for the Arria II GX DLL, as shown in
Table
frequency mode 0, 1, 2, and 3, the 6-bit DQS delay settings vary with PVT to
implement the phase-shift delay. In frequency modes 4 and 5, only 5 bits of the DQS
delay settings vary with PVT to implement the phase-shift delay; the MSB of the DQS
delay setting is set to 0.
Comparator
aload
Phase
and
7–5. Each frequency mode provides different phase-shift selections. In
Table
Delay Chains
upndninclkena
7–5.
upndnin
Up/Down
Counter
6
6
offsetdelayctrlout [5:0]
offsetdelayctrlout [5:0]
delayctrlout [5:0]
dqsupdate
(Note 1)
offsetdelayctrlin [5:0]
offsetdelayctrlin [5:0]
6
DQS Delay
Settings
addnsub
addnsub
Phase offset settings
from the logic array
Phase offset settings
from the logic array
( offset [5:0] )
(4)
6
6
Arria II GX Device Handbook, Volume 1
(dll_offset_ctrl_b)
(dll_offset_ctrl_a)
Control
Control
Phase
Phase
Offset
Offset
B
A
( offset [5:0] )
6
6
(offsetctrlout [5:0])
DLL0 phase offset
settings to bottom side,
DLL1 phase offset settings
(offsetctrlout [5:0])
to right and top side of the
device (3)
DLL0 phase offset
settings to top and right
side, DLL1 phase offset
settings to bottom side of
the device (3)
7–19