EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 221

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

© July 2010
AIIGX51009-3.0
Altera Corporation
This chapter contains information about the Arria
schemes, instructions about how to execute the required configuration schemes, and
all the necessary option pin settings. This chapter also reviews the different ways you
can configure your device and explains the design security and remote system
upgrade features for the Arria II GX devices.
This chapter includes the following sections:
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Arria II GX devices use SRAM cells to store configuration data. Because SRAM
memory is volatile, you must download configuration data to the Arria II GX device
each time the device powers up. You can configure Arria II GX devices using one of
four configuration schemes:
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All configuration schemes use either an external controller (for example, a MAX
device or microprocessor), a configuration device, or a download cable. For more
information about the configuration features, refer to
page
“Configuration Features”
“Power-On Reset Circuit and Configuration Pins Power Supply” on page 9–3
“Configuration Process” on page 9–4
“Configuration Schemes” on page 9–6
“Fast Passive Parallel Configuration” on page 9–8
“Active Serial Configuration (Serial Configuration Devices)” on page 9–14
“Passive Serial Configuration” on page 9–22
“JTAG Configuration” on page 9–29
“Device Configuration Pins” on page 9–34
“Configuration Data Decompression” on page 9–41
“Remote System Upgrades” on page 9–43
“Remote System Upgrade Mode” on page 9–47
“Dedicated Remote System Upgrade Circuitry” on page 9–49
“Quartus II Software Support” on page 9–54
“Design Security” on page 9–55
Fast passive parallel (FPP)
Active serial (AS)
Passive serial (PS)
JTAG
9–2.
9. Configuration, Design Security, and
Remote System Upgrades in Arria II GX
®
II GX supported configuration
“Configuration Features” on
Arria II GX Device Handbook, Volume 1
Devices
®
II