ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 109

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
12.3.4
Note:
1
2
3
4
5
6
The active transition is software programmable through the IEDGi bit in the control register
(CRi).
Timing resolution is one count of the free running counter: (
Procedure
To use the input capture function select the following in the CR2 register:
●
●
And select the following in the CR1 register:
●
●
When an input capture occurs:
●
●
●
Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1.
2.
After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never
be set until the ICiLR register is also read.
The ICiR register contains the free running counter value which corresponds to the most
recent input capture.
The two input capture functions can be used together even if the timer also uses the two
output compare functions.
In One Pulse mode and PWM mode only Input Capture 2 can be used.
The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any
transitions on these pins activates the input capture function.
Moreover if one of the ICAPi pins is configured as an input and the second one as an output,
an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.
This can be avoided if the input capture function i is disabled by reading the ICiHR
(see note 1).
The TOF bit can be used with interrupt generation in order to measure events that go
beyond the timer range (FFFFh).
Select the timer clock (CC[1:0]) (see
Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2
pin must be configured as floating input or input with pull-up without interrupt if this
configuration is available).
Set the ICIE bit to generate an interrupt after an input capture coming from either the
ICAP1 pin or the ICAP2 pin
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1pin must be configured as floating input or input with pull-up without interrupt if
this configuration is available).
ICFi bit is set.
The ICiR register contains the value of the free running counter on the active transition
on the ICAPi pin (see
A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC
register. Otherwise, the interrupt remains pending until both conditions become true.
Reading the SR register while the ICFi bit is set.
An access (read or write) to the ICiLR register.
Figure
Doc ID 12370 Rev 8
53).
Table
50).
f
CPU
/
CC[1:0]).
16-bit timer
109/324