ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 115

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
Note:
Note:
12.3.9
1
2
3
4
5
The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate
an Output Compare interrupt.
When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.
The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to
perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take
care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can
also generates interrupt if ICIE is set.
When One Pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time has been elapsed but cannot generate an
output waveform because the level OLVL2 is dedicated to the One Pulse mode.
Figure 57. One pulse mode timing example
Figure 58. Pulse width modulation mode timing example with 2 output compare
On timers with only one Output Compare register, a fixed frequency PWM signal can be
generated using the output compare and the counter overflow to define the pulse length.
Pulse width modulation mode
Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency
and pulse length determined by the value of the OC1R and OC2R registers.
Pulse Width Modulation mode uses the complete Output Compare 1 function plus the
OC2R register, and so this functionality can not be used when PWM mode is activated.
In PWM mode, double buffering is implemented on the output compare registers. Any new
values written in the OC1R and OC2R registers are taken into account only at the end of the
PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).
Note: OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1
Note: IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1
COUNTER 34E2
functions
OCMP1
COUNTER
OCMP1
ICAP1
IC1R
compare2
FFFC FFFD FFFE
01F8
Doc ID 12370 Rev 8
FFFC FFFD FFFE
OLVL2
OLVL2
compare1
01F8
2ED0 2ED1 2ED2
compare1
2ED0 2ED1 2ED2
OLVL1
OLVL1
2ED3
compare2
34E2
OLVL2
FFFC FFFD
2ED3
FFFC
OLVL2
16-bit timer
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