ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 155

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
Note:
Note:
Note:
14.8.2
Bit 4 = MSTR Master Mode
This bit is set and cleared by software. It is also cleared by hardware when, in master mode,
SS = 0 (see
Bit 3 = CPOL Clock Polarity
This bit is set and cleared by software. This bit determines the idle state of the serial Clock.
The CPOL bit affects both the master and slave modes.
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.
Bit 2 = CPHA Clock Phase
This bit is set and cleared by software.
The slave must have the same CPOL and CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency
These bits are set and cleared by software. Used with the SPR2 bit, they select the baud
rate of the SPI serial clock SCK output by the SPI in master mode.
These 2 bits have no effect in slave mode.
Table 58.
Control/status register (SPICSR)
Read/ write (some bits Read Only)
Reset value: 0000 0000 (00h)
Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only)
This bit is set by hardware when a transfer has been completed. An interrupt is generated if
SPIF
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are reversed.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
0: The first clock transition is the first data capture edge.
1: The second clock transition is the first capture edge.
7
Master mode fault
SPI master mode SCK frequency
WCOL
Serial clock
f
f
f
f
CPU
f
f
CPU
CPU
CPU
CPU
CPU
/128
/16
/32
/64
/4
/8
OVR
Doc ID 12370 Rev 8
(MODF)).
MODF
SPR2
1
0
1
0
-
Serial peripheral interface (SPI)
SOD
SPR1
0
1
SSM
SPR0
0
1
0
1
155/324
SSI
0