ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 235

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
We could simply wait for the end of the reception, but this could take a long time (200µs for a
100-bit frame at 500 kHz), so we also monitor the Rx pin of the microcontroller to minimize
the time the application may wait in the while loop.
We know the critical window is located at the end of the frame, 6+ CAN bit times after the
acknowledge bit (exactly six full bit times plus the time from the beginning of the bit to the
sample point). Those bits represent the acknowledge delimiter + the end of frame slot.
We know also that those 6+ bits are in recessive state on the bus, therefore if the CAN Rx
pin of the device is at ‘0’, (reflecting a CAN dominant state on the bus), this is early enough
to be sure we can release the FIFO before the critical time slot.
Therefore, if the device hardware pin Rx is at 0 and there is a reception on going, its
message will be transferred to the FIFO only 6+ CAN bit times later at the earliest (if the
dominant bit is the acknowledge) or later if the dominant bit is part of the message.
Compiled with Cosmic C compiler, the workaround generates the following assembly lines:
In the worst case configuration, if the CAN cell speed is set to the maximum baud rate, one
bit time is 8 CPU cycle. In this case the minimum time between the end of the acknowledge
and the critical period is 52 CPU cycles (48 for the 6 bit times + 4 for the (PROP SEG +
T
see the dominant state to the time we perform the FIFO release (one full loop + the actual
release) therefore the application will never release the FIFO at the critical time when this
workaround is implemented.
Timing analysis
●
Inside a CAN frame, the longest period that the Rx pin stays in recessive state is 5 bits. At
the end of the frame, the time between the acknowledge dominant bit and the end of
reception (signaled by REC bit status) is 8t
workaround is: 8t
At low speed, this time could represent a long delay for the application, therefore it makes
sense to evaluate how frequently this delay occurs.
In order to reach the critical FMP = 2, the CAN node needs to receive two messages without
servicing them. Then in order to reach the critical window, the cell has to receive a third one
and the application has to release the mailbox at the same time, at the end of the reception.
In the application, messages are not processed only if either the interrupt are disabled or
higher level interrupts are being serviced.
if ((CRFR & 0x03) == 0x02)
while
CRFR |= B_RFOM;
Seg1
_WHILELOOP:
_RELEASE:
Time spent in the workaround
). According to the previous code timing, we need less than 15 cycles from the time we
((CMSR & 0x20) && (CDGR & 0x08)) { };
CANbit
ld
and
cp
jrne
btjf
btjt
bset
+t
loop
a, CRFR
a,#3
a,#2
_RELEASE
CMSR,#5,_RELEASE
CDGR,#3,_WHILELOOP
CRFR,#5
+t
test
Doc ID 12370 Rev 8
+t
release
in this case or 8t
CANbit
Cycles
3
2
2
3
5
5
5
, therefore the maximum time spent in the
test: 10 cycles
loop: 10 cycles
release: 5 cycles
CANbit
beCAN controller (beCAN)
+25t
CPU
.
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