ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 137

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
Note:
1
2
3
1.
2.
3.
4.
If OLVL1 = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the
OC2R and OC1R registers.
If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.
The OC
the following formula:
Where:
t
f
PRESC
Table
The Output Compare 2 event causes the counter to be initialized to FCh (see
The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce
a timer interrupt if the ICIE bit is set and the I bit is cleared.
In PWM mode the ICAP1 pin can not be used to perform input capture because it is
disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be
CPU
Load the OC2R register with the value corresponding to the period of the signal using
the formula in the opposite column.
Load the OC1R register with the value corresponding to the period of the pulse if
(OLVL1 = 0 and OLVL2 = 1) using the formula in the opposite column.
Select the following in the CR1 register:
–
–
Select the following in the CR2 register:
–
–
–
55)
=
=
=
i
R register value required for a specific timing application can be calculated using
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC1R register.
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC2R register.
Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
Set the PWM bit.
Select the timer clock (CC[1:0]) (see
Signal or pulse period (in seconds)
Timer prescaler factor (2, 4, 8 or 8000 depending on CC[1:0] bits, see
PLL output x2 clock frequency in hertz (or f
Counter
= OC1R
Doc ID 12370 Rev 8
When
Counter
= OC2R
When
OCiR Value =
Pulse Width Modulation cycle
OCMP1 = OLVL2
OCMP1 = OLVL1
Counter is reset
ICF1 bit is set
Table
PRESC
to FCh
t
*
f
CPU
55).
- 5
OSC
/2 if PLL is not enabled)
8-bit timer (TIM8)
Figure
137/324
69)