ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 172

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

LINSCI serial communication interface (LIN master/slave)
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Bit 6 = TCIE Transmission complete interrupt enable
This bit is set and cleared by software.
Bit 5 = RIE Receiver interrupt enable.
This bit is set and cleared by software.
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
Bit 3 = TE Transmitter enable.
This bit enables the transmitter. It is set and cleared by software.
During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble (idle
line) after the current word.
When TE is set there is a 1 bit-time delay before the transmission starts.
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared by software.
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or not. It is set and cleared by software and
can be cleared by hardware when a wake-up sequence is recognized.
Before selecting Mute mode (by setting the RWU bit) the SCI must first receive a data byte,
otherwise it cannot function in Mute mode with wakeup by Idle line detection.
In address mark detection wake-up configuration (WAKE bit = 1) the RWU bit cannot be
modified by software while the RDRF bit is set.
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is set and cleared by software.
If the SBK bit is set to “1” and then to “0”, the transmitter will send a BREAK word at the end
of the current word.
Data register (SCIDR)
Read/ write
Reset value: Undefined
0: interrupt is inhibited
1: an SCI interrupt is generated whenever TC = 1 in the SCISR register
0: interrupt is inhibited
1: an SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR register
0: interrupt is inhibited
1: an SCI interrupt is generated whenever IDLE = 1 in the SCISR register.
0: transmitter is disabled
1: transmitter is enabled
0: receiver is disabled in the SCISR register
1: receiver is enabled and begins searching for a start bit
0: receiver in active mode
1: receiver in mute mode
0: no break character is transmitted
1: break characters are transmitted
Doc ID 12370 Rev 8
ST72561-Auto