ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 211

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
Note:
16.8.4
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is set and cleared by software.
If the SBK bit is set to “1” and then to “0”, the transmitter sends a BREAK word at the end of
the current word.
Control Register 3 (SCICR3)
Read/ write
Reset value: 0000 0000 (00h)
Bit 7 = Reserved, must be kept cleared.
Bit 6 = LINE LIN Mode Enable.
This bit is set and cleared by software.
The LIN Master mode enables the capability to send LIN Synch Breaks (13 low bits) using
the SBK bit in the SCICR2 register.
In transmission, the LIN synch break low phase duration is shown as below:
Table 75.
Bits 5:4 = Reserved, forced by hardware to 0.
These bits are not used.
Bit 3 = CLKEN Clock Enable.
This bit allows the user to enable the SCLK pin.
Bit 2 = CPOL Clock Polarity.
This bit allows the user to select the polarity of the clock output on the SCLK pin. It works in
conjunction with the CPHA bit to produce the desired clock/data relationship (see
and
Figure
0: no break character is transmitted
1: break characters are transmitted
0: LIN mode disabled
1: LIN master mode enabled
0: SLK pin disabled
1: SLK pin enabled
0: steady low value on SCLK pin outside transmission window.
1: steady high value on SCLK pin outside transmission window.
7
-
LINE
0
1
93).
LIN sync break duration
LINE
M
0
1
0
1
-
Doc ID 12370 Rev 8
LINSCI serial communication interface (LIN master only)
-
Number of low bits sent during a LIN synch break
CLKEN
CPOL
10
11
13
14
CPHA
Figure 92
LBCL
211/324
0