ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 245

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ST72561J9-Auto

Manufacturer Part Number
ST72561J9-Auto
Description
8-bit MCU for automotive
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72561J9-Auto

Hdflash Endurance
100 cycles, data retention 20 years at 55 °C
5 Power Saving Modes
halt, auto wake up from halt, active halt, wait and slow
ST72561-Auto
Note:
Transmit Error Counter Register (TECR)
Read only
Reset value: 0000 0000 (00h)
TEC[7:0] is the least significant byte of the 9-bit transmit error counter implementing part of
the fault confinement mechanism of the CAN protocol.
Receive Error Counter Register (RECR)
Page: 00h — read only
Reset value: 0000 0000 (00h)
REC[7:0] is the receive error counter implementing part of the fault confinement mechanism
of the CAN protocol. In case of an error during reception, this counter is incremented by 1 or
by 8 depending on the error condition as defined by the CAN standard. After every
successful reception the counter is decremented by 1 or reset to 120 if its value was higher
than 128. When the counter value exceeds 127, the CAN controller enters the error passive
state.
CAN diagnosis register (CDGR)
Read/ write
Reset value: 0000 1100 (0Ch)
All bits of this register are set and cleared by software.
Bit 3 = RX CAN Rx Signal
Read
Monitors the actual value of the CAN_RX Pin.
Bit 2 = SAMP Last Sample Point
Read
The value of the last sample point.
Bit 1 = SILM Silent Mode
Read/Set/Clear
REC7
TEC7
0: normal operation
1: silent mode
7
7
7
0
REC6
TEC6
0
REC5
TEC5
0
Doc ID 12370 Rev 8
REC4
TEC4
0
REC3
TEC3
RX
SAMP
REC2
TEC2
beCAN controller (beCAN)
REC1
TEC1
SILM
REC0
LBKM
TEC0
245/324
0
0
0

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