ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 83

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
Note:
Figure 34. Watchdog block diagram
The application program must write in the WDGCR register at regular intervals during
normal operation to prevent an MCU reset. This operation must occur only when the counter
value is lower than the window register value. The value to be stored in the WDGCR register
must be between FFh and C0h (see
●
●
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
●
Enabling the watchdog:
when Software Watchdog is selected (by option byte), the watchdog is disabled after a
reset. It is enabled by setting the WDGA bit in the WDGCR register, then it cannot be
disabled again except by a reset.
When Hardware Watchdog is selected (by option byte), the watchdog is always active
and the WDGA bit is not used.
Controlling the downcounter:
this downcounter is free-running: It counts down even if the watchdog is disabled.
When the watchdog is enabled, the T6 bit must be set to prevent generating an
immediate reset.
The T[5:0] bits contain the number of increments which represents the time delay
before the watchdog produces a reset (see
minimum and a maximum value due to the unknown status of the prescaler when
writing to the WDGCR register (see
The window register (WDGWR) contains the high limit of the window: To prevent a
reset, the downcounter must be reloaded when its value is lower than the window
register value and greater than 3Fh.
process.
Watchdog Reset on Halt option:
if the watchdog is activated and the watchdog reset on halt option is selected, then the
HALT instruction will generate a Reset.
RESET
f
OSC2
MCC/RTC
11
MSB
Write WDGCR
RTC COUNTER
12-BIT MCC
T6:0 > W6:0 CMP
comparator
DIV 64
Doc ID 12370 Rev 8
= 1 when
6
5
LSB
WDGA
Figure
-
0
Figure
Figure 37
TB[1:0] bits
(MCCSR
Register)
W6
T6
35):
W5
WATCHDOG WINDOW REGISTER (WDGWR)
T5
WATCHDOG CONTROL REGISTER (WDGCR)
36).
Figure
6-BIT DOWNCOUNTER (CNT)
describes the window watchdog
W4
T4
WDG PRESCALER
35). The timing varies between a
W3
DIV 4
T3
Window watchdog (WWDG)
W2
T2
W1
T1
W0
T0
83/324