ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 130

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

8-bit timer (TIM8)
13.3.2
Note:
130/324
1
2
3
4
5
Input capture
In this section, the index, i, may be 1 or 2 because there are two input capture functions in
the 8-bit timer.
The two 8-bit input capture registers (IC1R and IC2R) are used to latch the value of the free
running counter after a transition is detected on the ICAPi pin (see
ICiR register is a read-only register.
The active transition is software programmable through the IEDGi bit of Control Registers
(CRi).
Timing resolution is one count of the free running counter (see
Procedure
To use the input capture function select the following in the CR2 register:
●
●
And select the following in the CR1 register:
●
●
When an input capture occurs:
●
●
●
Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1.
2.
The ICiR register contains the free running counter value which corresponds to the most
recent input capture.
The two input capture functions can be used together even if the timer also uses the two
output compare functions.
Once the ICIE bit is set both input capture features may trigger interrupt requests. If only
one is needed in the application, the interrupt routine software needs to discard the
unwanted capture interrupt. This can be done by checking the ICF1 and ICF2 flags and
resetting them both.
In One pulse Mode and PWM mode only Input Capture 2 can be used.
The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any
transitions on these pins activates the input capture function.
Select the timer clock (CC[1:0]) (see
Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2
pin must be configured as floating input or input with pull-up without interrupt if this
configuration is available).
Set the ICIE bit to generate an interrupt after an input capture coming from either the
ICAP1 pin or the ICAP2 pin
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1
pin must be configured as floating input or input with pull-up without interrupt if this
configuration is available).
ICFi bit is set.
The ICiR register contains the value of the free running counter on the active transition
on the ICAPi pin (see
A timer interrupt is generated if the ICIE bit is set and the interrupt mask is cleared in
the CC register. Otherwise, the interrupt remains pending until both conditions become
true.
Reading the SR register while the ICFi bit is set.
An access (read or write) to the ICiR register.
Figure
Doc ID 12370 Rev 8
64).
Table
55).
Table
Figure
55).
63).
ST72561-Auto